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| GIM>Research>project>FP7 216807 SATURN... |
| PROJECT: |
| | FP7 216807 SATURN |
| Select this link to see PUBLICATIONS within this project |
| |
| Title: | FP7 216807 SATURN |
| Acronym: | |
| Payer: | FP7 ICT EC |
| Partners: | Artisan, Extessy AG, Intracom, Thales, Paderborn University |
| Budget: | 193200€ |
Years, begin: | 2008 |
end: | 2010 |
| Director: | Eugenio Villar |
| R&D Lines: |
Design and verification of HW/SW embedded systems
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| Staff: |
Eugenio Villar
Pablo Peñil
Pablo Garralda
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| Description: | The main objective of the SATURN project is to bridge the current gap between modelling and verification/synthesis in UML based designs of Embedded Systems which are equally composed of HW and SW. To do this, the UML profile for Modeling and Analysis of Real-Time and Embedded systems (MARTE) is evaluated for its complementary application with SysML and significantly improved towards the formal semantics of different Models of Computation for integrated modelling and verification environments. By bridging the gap between modelling and verification, the SATURN project expects a significant reduction in time-to-market. This will be delivered through: (a) the augmentation of SysML with MARTE, (b) the use of MARTE as a basic platform to integrate SysML with a run-time environment for cross-domain verification, (c) the automatic generation of implementable descriptions for both hardware (SystemC/VHDL) and embedded software (C/C++) components of the targeted system, as well as (d) the integration of different abstraction layers allowing seamless integration at functional and target architecture level. Results are validated by two complex industrial proof-of-concept case studies covering a smart camera system and an outdoor broadband wireless telecom system.
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