Microelectronics Engineering Group

Microelectronics Engineering Group

 Electronics Technology, Systems and Automation Engineering Department University of Cantabria
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Title:The Level-0 VHDL Synthesis Syntax and Semantics - 2nd Part
Type:International Paper
Where:The VHDL Newsletter, No. 20, pp.1 and 12
Date:1995-12
Authors: Eugenio Villar
R&D Lines: Design and verification of electronic systems for communications
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