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Title:	VHDL multi-wait descriptions for synthesis
Type:	International Paper
Where:	Working Conference of VHDL Forum for CAD in Europe, Dresden Germany, pp 59-69
Date:	1996-04
Authors:	W. Ecker Eugenio Villar
R&D Lines:	Design and verification of electronic systems for communications
Projects:
ISBN:	3-8265-1462-9
PDF File:
Abstract:


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