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| Title: | AADL simulation and performance analysis in SystemC |
| Type: | International Conference |
| Where: | 14th IEEE International Conference on Engineering of Complex Computer Systems, Postdam |
| Date: | 2009-06 |
| Authors: |
Roberto Varona
Eugenio Villar
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| R&D Lines: |
Design and verification of HW/SW embedded systems
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| Projects: |
ITEA 05015 SPICES
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| ISBN: | 978-0-7695-37023 |
| PDF File: |
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| Abstract: | Due to the increasing complexity of embedded systems, new design methodologies have to be adopted, since traditional techniques are no longer efficient. Model-based engineering enables the designer to confront these concerns using the architecture description of the system as the main axis during the design cycle. Defining the architecture of the system before its implementation enables the analysis of constraints imposed on the system from the beginning of the design cycle until the final implementation. AADL has been proposed for designing and analyzing SW and HW architectures for real-time mission-critical embedded systems. Although the Behavioral Annex improves its simulation semantics, AADL is a language for analyzing architectures and not for simulating them. In this paper, AADS, an AADL simulation tool is presented. AADS supports the performance analysis of the AADL specification throughout the refinement process from the initial system architecture until the complete, detailed application and execution platform are developed. In this way, AADS enables the verification of the initial timing constraints during the complete design process.
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