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Title: | Formal Support for Untimed SystemC specifications: Application to high-level synthesis |
Type: | International Conference |
Where: | Forum on specification & Design Languages 2010, FDL'2010, IEEE |
Date: | 2010-09 |
Authors: |
Víctor Fernández
Fernando Herrera
Eugenio Villar
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R&D Lines: |
Design and verification of HW/SW embedded systems
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Projects: |
IST 033511 ANDRES
FP7 IP 247999 COMPLEX
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ISBN: | 1636-9874 |
PDF File: | see file
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Abstract: | SystemC lacks a well defined formal semantics for abstract
specification, specifically for untimed models. This paper tackles
this problem by providing the fundamentals of a framework which
enables the analysis of any untimed SystemC specification under a
formal meta-model. Then, the conditions for the SystemC
specification to correspond with its formal meta-model are
defined. As an application example, the use of the framework for
high-level synthesis verification is shown.
IEEEXplore FDL'10 Proceedings
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