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| Title: | SW Annotation Techniques and RTOS Modeling for Native Simulation of Heterogeneous Embedded Systems |
| Type: | Book chapter |
| Where: | Kiyofumi Tanaka: "Embedded Systems - Theory and Design Methodology", InTech, Croatia |
| Date: | 2012-02 |
| Authors: |
Héctor Posadas
Álvaro Díaz
Eugenio Villar
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| R&D Lines: |
Design and verification of HW/SW embedded systems
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| Projects: |
FP7 IP 247999 COMPLEX
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| ISBN: | 978-953-51-01673 |
| PDF File: |
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| Abstract: | In this chapter SW Annotation Techniques and RTOS Modelling for Native Simulation of Heterogeneous Embedded Systems are proposed. A complete SW platform is not required, since the native SW platform can be partially used. Capabilities for modeling the delay of the SW execution in the target processor, the operation of the different level of caches, the target operating system and the other components in the HW platform, have been added. In order to enable the designers to adjust the speed/accuracy ratio according to their needs, different solutions for SW annotation are presented and analyzed in the chapter. A basic OS modeling infrastructure was developed. This infrastructure has been extended to support other APIs such as Win32. This is an important step ahead to the state of the art, since very few proposed infrastructures support real operating systems, and to the best of our knowledge none of them considers these different APIs. The resulting virtual platforms are only two-three times slower that functional execution when caches are not considered, and about one order of magnitude slower when using accurate cache models. Processor modeling accuracy in terms of execution times is lower than 5% of error and the number of cache misses has an error of about 10%.
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