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| PUBLICATION |
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| Title: | Towards a Verification Flow Across Abstraction Levels: Verifying Implementations Against Their Formal Specification |
| Type: | International Paper |
| Where: | TCAD |
| Date: | 2017-03 |
| Authors: |
Pablo González
Pablo Pedro Sánchez
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| R&D Lines: |
Verification of Embedded Systems
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| Projects: |
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| ISBN: | |
| PDF File: |
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| Abstract: | The use of formal models to describe early versions
of the structure and the behavior of a system has become common
practice in industry. UML and OCL are the de-facto specification
languages for these tasks. They allow for capturing system
properties and module behavior in an abstract but still formal
fashion. At the same time, this enables designers to detect errors
or inconsistencies in the initial phases of the design flow – even if
the implementation has not already started. Corresponding tools
for verification of formal models got established in the recent
past. However, verification results are usually not re-used in
later design steps anymore. In fact, similar verification tasks are
applied again, e. g., after the implementation has been completed.
This is a waste of computational and human effort.
In this work, we address this problem by proposing a method
which checks a given implementation of a system against its
corresponding formal method. This allows for transferring verification
results already obtained from the formal model to the
implementation and, eventually, motivates a new design flow
which addresses verification across abstraction levels. The paper
describes the applied techniques as well as their orchestration.
Afterwards, the applicability of the proposed methodology is
demonstrated by means of examples as well as a case study
from an industrial context. |
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