| Ficha completa |
| Título: | Efficient Implementation of Pattern Matching
Recognition in Heterogeneus Architectures |
| Tipo: | Publicacion en Proceedings o Actas nacionales |
| Lugar: | XXIX Conference on Design of Circuits and Integrated Systems, DCIS 2014 |
| Fecha: | 2014-11 |
| Autores: |
Javier González Bayón
Pablo Pedro Sánchez
Javier Barreda
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| Líneas: |
Diseño y verificación de sistemas embebidos HW/SW
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| Proyectos: |
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| ISBN: | |
| Fichero: | ver fichero
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| Resumen: | Implementation of pattern recognition algorithms
is an important and complex task. These schemes usually
perform time and resource consuming operations as 2D FFT.
That is the reason why usually they are implemented in
heterogeneous platforms with at least one DSP that accelerates
the mathematical applications. Nevertheless, even using this
specific processor the execution time required can be excessive.
Therefore, an efficient use of all the processors available in the
platform is mandatory. This paper proposes an efficient
implementation of pattern recognition schemes in a
heterogeneous platform that includes an ARM processor and a
DSP. |
