| Abstract: | Verifying the correctness of multi-processing embedded systems is a complex task. In order to avoid the cost, effort and time that the direct design verification on a physical prototype implies, simulation on a virtual model of the system is the most popular method used currently. Commercially available simulators require the complete SW binaries to be executed on each processing node. Although they can provide very accurate results, they can only be applied once the SW development has been completed. Native simulation technologies have been proposed to generate virtual platforms at the beginning of the design process, reducing porting efforts. As with any Discrete-Event simulation technique, native simulation presents problems in order to take advantage of the multi-processing capabilities of current host workstations where the simulation will be executed. Several concurrent simulated threads can be run in parallel in the host but to ensure deterministic behavior, it is necessary to synchronize all of them periodically in order to maintain causality among events. As a consequence, the number of cores that can be active during simulation is dramatically reduced. Embedded SW requires specific simulation techniques to take advantage of the multi-processing capabilities of workstations and to efficiently parallelize the simulation. In this paper, the results of the research effort towards an efficient, accurate-enough,parallel implementation of native simulation is presented.
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