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| GIM>Investigación>Publicaciones |
| PUBLICACIONES en las que participa: "Víctor Fernández" ordenadas por línea de investigación |
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| Diseño y verificación de sistemas electrónicos para comunicaciones |
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J. Pérez, V. Fernández
"3GPP2/802.20 RC/QC-LDPC Encoding"
IEEE European Wireless 2010, Lucca, Italy. 2010-04 |
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J. Pérez, V. Fernández
"Codificador ldpc e interleaver para dvb-s2"
Oficina Española de Patentes y Marcas. OEPM . 2009-09 |
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J. Pérez, V. Fernández
"Reducing the error floor using a two-level permutation in structured eIRA LDPCs"
XIX Conference on Design of Circuits and Integrated Systems (DCIS2008), Grenoble, France. 2008-11 |
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J. Pérez, V. Fernández
"Low-Cost Enconding of IEEE 802.11n"
IET Electronics Letters
Volume 44, Issue 4, pp. 307-308. 14 Feb 2008. 2008-03 |
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J. Pérez, V. Fernández, Fernando Vallejo, Ana Jalón
"Novel DVB-S2 FEC Encoder Architecture"
9th International Workshop on Signal Processing for Space Communications. ESTEC, Noordwijk, The Netherlands. 2006-09 |
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J. Pérez, V. Fernández
"Improved Architectures for VLC MAP decoders"
IEEE International Symposium on Wireless Communication Systems (ISWCS), Valencia, Spain. 2006-09 |
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J. Pérez, V. Fernández
"Hierarchical and Pseudo-Random eIRA Codes Based on BIBDs and Primitive Interleavers"
IEEE International Conference on Wireless Information Networks and Systems, Setubal, Portugal. 2006-08 |
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J. Pérez, V. Fernández
"Near Random Performance of Structured eIRA Codes"
IEEE and IEE co-sponsored Signal Processing for Wireless Communications (SPWC) Workshop, London. 2006-05 |
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J. Pérez, V. Fernández
"Hardware Aware eIRA LDPC Code Generation"
IEEE International Symposium of Wireless Communication Systems 2005(ISWCS 2005), Siena, Italy. 2005-09 |
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J. Pérez, V. Fernández
"Optimizations in max-log-map LLRe VLSI architecture"
IEEE International Symposium on Signals, Circuits and Systems (ISSCS). Iasi (Romania)
. 2005-07 |
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J. Pérez, V. Fernández
"Optimizations in DVB-RCS Turbo Decoder Based on Trellis Structure"
XIX Conference on Design of Circuits and Integrated Systems (DCIS2004). Bordeaux. 2004-09 |
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J. Pérez, V. Fernández, H. Posadas, V. Fernández
"Estudio de viabilidad de DVB-S2 en Banda Ka"
Memoria técnica justificativa del proyecto PROFIT PNE-001/2003-EMP. 2004-04 |
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J. Pérez, P. Sánchez, V. Fernández
"FGPA Implementation of a MAP Decoder for DVB-S Satellite Reception"
XVIII Conference on Design of Circuits and Integrated Systems (DCIS2003). Ciudad Real. 2003-11 |
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V. Fernández, A. Jalón, L. Berrojo, Yves Leroy
"Design, Functional Verification and Test of a MPEG2-TS Multiplexer for an On-Board Satellite Processor"
XVII Conference on Design of Circuits and Integrated Systems (DCIS 2002). Santander. 2002-11 |
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V. Fernández, L. Berrojo, J. Prat, Y. Leroy
"Verification of a Digital Video Broadcasting Satellite System"
16th Design of Circuits and Integrated Systems Conference, DCIS 2001. Oporto (Portugal). 2001-11 |
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J. L. Barreda, I. Hidalgo, V. Fernández, P. Sánchez, E. Villar
"Fault Modeling in VITAL"
Proceedings of the Workshop on Libraries, Component Modeling, and Quality Assurance. Nantes, France. 1995-04 |
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| Diseño y verificación de sistemas embebidos HW/SW |
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E. Villar, P. Martínez, F. Alcalá, P. Sánchez, V. Fernández
"Método y sistema de localización espacial mediante marcadores luminosos para cualquier ambiente"
Oficina Española de Patentes y Marcas, OEPM. 2015-11 |
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R. Varona, V. Fernández, E. Villar
"HWSW Co-Design Survey"
Deliverable R1-2 of the ESTEC HW/SW Co-Design Project. 2011-05 |
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V. Fernández, F. Herrera, E. Villar
"Formal Support for Untimed SystemC specifications: Application to high-level synthesis"
Forum on specification & Design Languages 2010, FDL'2010, IEEE. 2010-09 |
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J. Pérez, V. Fernández, P. Sánchez
"Optimizing Data-Flow Graphs with Min/Max, Adding and Relational Operations"
Design Automation and Test in Europe 2010, DATE'10. 2010-03 |
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H. Posadas, J. Castillo, D. Quijano, V. Fernández, E. Villar, Marcos Martínez (DS2)
"SystemC Platform Modeling for Behavioral Simulation and Performance Estimation of Embedded Systems"
L. Gomes and J. M. Fernandes (Eds.): “Behavioral Modeling for Embedded Systems and Technologies: Applications for Design and Implementation”, IGI Global. 2009-07 |
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V. Fernández, E. Villar
"SystemC"
ARTIST Survey of Programming Languages.
Alan Burns (Editor). 2008-08 |
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H. Posadas, F. Herrera, V. Fernández, P. Sánchez, E. Villar, F. Blasco
"Single Source Design Environment for Embedded Systems Based on SystemC"
Design Automation for Embedded Systems, V.9, N.4, Springer, pp.293-312. 2004-12 |
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F. Herrera, V. Fernández, P. Sánchez, E. Villar
"Embedded Software Generation from SystemC for Platform Based Design"
"SystemC Methodologies and Applications", Kluwer Academic Publishers. 2003-01 |
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V. Fernández, F. Herrera, P. Sánchez, E. Villar
"Conclusiones: Metodología industrial de diseño de sistemas embebidos HW/SW"
Documento Entregable DF del proyecto FEDER 1FD97-0791. 2002-02 |
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V. Fernández, E. Villar, F. Herrera
"System-Level Specification in SystemC of a Residential Gateway"
16th Design of Circuits and Integrated Systems Conference, DCIS 2001. Oporto (Portugal). 2001-11 |
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F. Herrera, V. Fernández
"Introduction to SystemC"
"Design of HW/SW Embedded Systems". (Ed. E. Villar), Servicio de Publicaciones de la Universidad de Cantabria. 2001-07 |
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V. Fernández, F. Herrera, E. Villar
"Especificación ejecutable del demostrador industrial"
Documento Entregable R2-C2 del proyecto FEDER 1FD97-0791. 2001-04 |
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F. Herrera, V. Fernández, R. Rodríguez, P. Sánchez, E. Villar
"Especificación del demostrador industrial"
Documento Entregable R2-C1 del proyecto FEDER 1FD97-0791. 2000-10 |
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F. Herrera, R. Rodríguez, V. Fernández, E. Villar
"Desarrollo de Metodologías Industriales de Diseño de Sistemas Embebidos HW/SW"
I Seminario del Programa Nacional de Tecnologías de la Información y las Comunicaciones (TEDEA 2000). Almagro (Ciudad Real). 2000-09 |
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V. Fernández
"Síntesis de Alto Nivel de Sistemas Digitales Altamente Testables"
Tesis Doctoral. Universidad de Cantabria.. 1998-09 |
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V. Fernández, P. Sánchez
"A Novel Approach To High-Level Test Synthesis Based On Controller Redefinition"
Proceedings of the European Test Workshop. Sitges, Spain. 1998-05 |
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V. Fernández, P. Sánchez
"Advanced Techniques for EMBEDDED SYSTEMS DESIGN & TEST, Capítulo 9, TEST SYNTHESIS OF DIGITAL SYSTEMS. "
Kluwer Academic Publishers. 1998-01 |
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V. Fernández, P. Sánchez
"High-Level Test Synthesis based on controller redefinition"
IEE Electronics Letters, Vol. 33, No. 19, pp. 1596-1597. 1997-09 |
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V. Fernández, P. Sánchez
"Test Points Insertion For High-Level Test Synthesis"
Proceedings of the 4th Belsign Workshop. Santander, Spain. 1996-10 |
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V. Fernández, P. Sánchez
"Partial Scan High-Level Synthesis"
European Design & Test Conference. Paris, France. 1996-03 |
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V. Fernández, P. Sánchez, E. Villar
"A Novel High-Level Allocation Technique for Test"
Fourth Annual Atlantic Test Workshop. Corsica, France. 1995-07 |
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V. Fernández, P. Sánchez, E. Villar
"Partial Scan High-Level Synthesis Strategy"
Second International Test Synthesis Workshop. Santa Barbara, CA (USA). 1995-05 |
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V. Fernández, P. Sánchez, Marta García, E. Villar
"Fault Modeling and Injection in VITAL Descriptions"
Proceedings of the Third Annual Atlantic Test Workshop, Nimes, France. 1994-06 |
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V. Fernández, P. Sánchez, E. Villar
"High Level Synthesis Guided by Testability Measures"
First International Test Synthesis Workshop, Santa Barbara, CA (USA). 1994-05 |
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E. Villar, P. Sánchez, V. Fernández
"High Level Synthesis with Testability Criteria"
2nd IEEE Annual Atlantic Test Workshop, Hanover, USA. 1993-06 |
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