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| GIM>Investigación>Publicaciones |
| PUBLICACIONES ordenadas por línea de investigación |
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| Diseño de circuitos electrónicos de aplicación industrial |
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R. Casanueva, F. Azcondo, Lidia Alcedo, Jorge Jiménez
"Advanced Cutting Experiences for a Nuclear Power Plant Application"
IEEE Transactions on Industry Applications. 2010-01 |
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J. Pérez, P. Sánchez
"Real-Time Stereo Matching using memory-efficient Belief Propagation for High-definition 3D tele-presence systems"
Iberoamerican Congress on Pattern Recognition (CIARP-2009). Guadalajara, Mexico. 2009-11 |
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C. Brañas, F. Azcondo, R. Casanueva
"Simplified Analysis of a PWM-controlled Parallel Resonant Inverter for Electronic Ballast Applications"
The 35th Annual Conference of the IEEE Industrial Electronics Society, IECON 09, Oporto, Portugal. 2009-11 |
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R. Casanueva, F. Azcondo, F. Díaz, C. Brañas
"DC and Pulsed DC TIG Welding with a Scalable Power Supply"
2009 IEEE Industry Applications Society Annual Meeting, Houston, TX, EE.UU.. 2009-10 |
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C. Brañas, F. Azcondo, R. Casanueva
"Reduced Order Model for Envelope and Small-Signal Analysis of a Phase-Controlled Triple LCpCs Resonant Inverter for Electronic Ballast Applications"
2009 IEEE Industry Applications Society Annual Meeting. 2009-10 |
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F. Díaz, F. Azcondo, R. Casanueva, C. Brañas
"Microcontroller software applied to electronic ballast design"
European Conference on Power Electronics and Applications, EPE 2009. 2009-09 |
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C. Brañas, F. Azcondo, R. Casanueva
"Envelope modeling and small-signal analysis of a PWM-controlled parallel resonant inverter for electronic ballast applications"
IEEE Energy Conversion Congress and Exposition (ECCE 09), San José, CA, EE.UU.. 2009-09 |
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F. Díaz, Ryan Schnell, C. Brañas, F. Azcondo, Regan Zane, R. Casanueva
"Control digital de fase para el encendido resonante de lámparas de alta intensidad de descarga, utilizando núcleo de saturación suave"
Seminario Anual de Automática, Electrónica Industrial e Instrumentación, SAAEI 2009. 2009-07 |
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F. Azcondo, C. Brañas, R. Casanueva, F. Díaz
"Flexible power architecture for high quality welding application"
International Exhibition & Conference for Power Electronics, Intelligent Motion, Power Quality, PCIM Europe 2009. Nüremberg, Alemania. 2009-05 |
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C. Brañas, F. Azcondo, R. Casanueva
"Envelope Analysis of a Phase-Controlled Triple LCpCs Resonant Inverter for Electronic Ballast Applications"
2008 IEEE Industry Applications Society Annual Meeting (IAS 08), Edmonton, Canada. 2008-10 |
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F. Díaz, F. Azcondo, R. Casanueva, C. Brañas, R. Zane
"Digital control of a low-frequency square-wave electronic ballast with resonant ignition"
IEEE Transactions Industrial Electronics. 2008-09 |
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R. Casanueva, F. Azcondo, C. Brañas
"Generador de impulsos bipolar de electroerosión basado en un inversor resonante"
XV Seminario Anual de Automática, Electrónica Industrial e Instrumentación, SAAEI’08, Cartagena, España. 2008-09 |
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F. Díaz, F. Azcondo, R. Zane, R. Casanueva, C. Brañas
"Balasto electrónico LFSW con convertidor SEPIC de bobinas acopladas actuando como CFP y fuente de potencia"
XV Seminario Anual de Automática, Electrónica Industrial e Instrumentación, SAAEI’08, Cartagena, España. 2008-09 |
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C. Brañas, F. Azcondo, R. Casanueva
"A Generalized Study of Multi-Phase Parallel Resonant Inverters for High-Power Applications"
IEEE Transactions on Circuits and Systems I, vol. 55, pp. 2128-2138. 2008-08 |
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F. Azcondo, A. de Castro
"Power factor correction controllers based on current rebuilding technique implemented on FPGA"
International Exhibition & Conference for Power Electronics, Intelligent Motion, Power Quality, PCIM Europe 2008. Nüremberg, Alemania. 2008-05 |
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R. Casanueva, F. Azcondo, C. Brañas
"A new bipolar power supply for spark erosion based on a series-parallel resonant inverter"
2008 IEEE Applied Power Electronics Conference and Exhibition (APEC 2008), Austin, TX, EE.UU.. 2008-02 |
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R. Casanueva, L. Alcedo, F. Azcondo, J. Jiménez
"Advanced Cutting Experiences for a Nuclear Power Plant Application"
2007 IEEE Industry Applications Society Annual Meeting (IAS 2007), New Orleans, EE.UU.. 2007-09 |
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C. Brañas, F. Azcondo, R. Casanueva, F. Díaz
"Penta-phase Series-Parallel LCsCp Resonant Inverter to drive 1kW HPS Lamps"
2007 IEEE Industry Applications Society Annual Meeting (IAS 2007), New Orleans, EE.UU.. 2007-09 |
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F. Díaz, F. Azcondo, C. Brañas, R. Casanueva, R. Zane
"Digitally controlled low frequency square wave electronic ballast with resonant ignition and power loop"
2007 IEEE Industry Applications Society Annual Meeting (IAS 2007), New Orleans, EE.UU.. 2007-09 |
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F. Azcondo, A. Ortiz, M. Mañana, F. Díaz, C. Brañas, C. Renedo, S. Pérez, F. Delgado, R. Casanueva
"Effects of Flicker on Different Types of 150-W High-Pressure Sodium Lamps and Ballasts"
2007 IEEE Industry Applications Society Annual Meeting (IAS 2007), New Orleans, EE.UU.. 2007-09 |
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F. Díaz, F. Azcondo, R. Casanueva, C. Brañas
"Diseño de balasto electrónico resonante con corrector de factor de potencia actuando como fuente de potencia para alimentar lámparas de halogenuros metálicos"
XIV Seminario Anual de Automática, Electrónica Industrial e Instrumentación, SAAEI’07, Puebla, Mexico. 2007-09 |
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R. Casanueva, H.-P. Schulze, F. Azcondo, M. Leone
"Fuentes de alimentación de electroerosión: aplicaciones y propuestas"
2nd Manufacturing Engineering Society International Conference MESIC- CISIF’07, Madrid, España. 2007-07 |
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R. Casanueva, F. Azcondo, C. Brañas
"Output Current Sensitivity Analysis of the LCpCs Resonant Inverter: Current Source Design Criteria"
IEEE Transactions on Industrial Electronics, vol. 54, pp. 1560-1568. 2007-06 |
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F. Díaz, F. Azcondo, C. Brañas, R. Casanueva, R. Zane
"Control of low-frequency square-wave electronic ballast with resonant ignition using a dsPIC30F2010"
2007 IEEE International Symposium on Industrial Electronics, ISIE 2007. 2007-06 |
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M. Mañana, A. Ortiz, C. Renedo, S. Pérez, F. Delgado, F. Azcondo, F. Díaz, C. Brañas, R. Casanueva
"Comparison of flicker sensitivity in HPS lamps"
2007 IEEE International Symposium on Industrial Electronics, ISIE 2007. 2007-06 |
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C. Brañas, F. Azcondo, R. Casanueva
"Phase-controlled quadruple LCp resonant inverter to drive 600W HPS lamps"
IEEE Transactions on Power Electronics, vol. 22, pp. 831-838. 2007-05 |
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F. Azcondo, F. Díaz, C. Brañas, R. Casanueva
"New Devices for Power Correction Applications"
International Conference for Power Electronics, Intelligent Motion, Power Quality, PCIM Europe 2007, Nüremberg, Alemania. 2007-05 |
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R. Casanueva, F. Azcondo, C. Brañas
"AC Current Source Resonant Inverter for an EDM Power Supply"
International Symposium on Electromachining (ISEM XV), Pittsburgh, EE.UU.. 2007-04 |
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F. Azcondo, F. Díaz, R. Casanueva, C. Brañas
"Microcontroller power mode stabilized power factor correction stage for electronic ballast applied to metal halide lamps"
Proc. of the 32nd Annual Conference of IEEE Industrial Electronics Society, pp. 1733-1738. Paris, Francia. 2006-11 |
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F. Díaz, F. Azcondo, R. Casanueva, C. Brañas, Regan Zane
"Balasto electrónico de onda cuadrada de baja frecuencia con encendido resonante, utilizando control digital en modo potencia"
Actas del XIII Seminario Annual de Automática, Electrónica Industrial e Instrumentación. Gijón, España. 2006-09 |
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C. Brañas, F. Azcondo, R. Casanueva
"A Generalized Study of Multi-Phase Parallel Resonant Inverters for High Power Applications"
Proc. of the IEEE International Symposium on Circuit and Systems, pp. 2265-2268. Kos, Grecia.. 2006-05 |
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R. Casanueva, F. Azcondo, C. Brañas, S. Bracho
"High Spark, Low Loss. Paralleled LCsCp Resonant Converters for Spark Erosion Applications"
IEEE Industry Applications Magazine. 2006-04 |
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F. Azcondo, F. Díaz, R. Casanueva, C. Brañas, Regan Zane
"Low frequency square-wave electronic ballast with resonant ignition using digital mode and power control"
IEEE Applied Power Electronics Conference and Exhibition, APEC 2006. Dallas, Texas (EE.UU.). 2006-03 |
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C. Brañas, F. Azcondo, R. Casanueva, S. Bracho
"Phase-controlled quadruple LCp resonant inverter to drive 600W HPS lamps"
IEEE Applied Power Electronics Conference and Exhibition, APEC 2006. Dallas, Texas (EE.UU.). 2006-03 |
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C. Brañas, F. Azcondo, S. Bracho
"Design of LCpCs Resonant Inverters as a Power Source for HID Lamp Ballast Applications"
IEEE Transaction on Industry Applications 41 (6): 1584-1595 . 2005-11 |
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Markus Laüter, R. Casanueva, Hans-Peter Schulze, F. Azcondo, Günter Wollenberg
"Development trends of process energy sources for special applications of the spark erosion"
Nonconventional Technologies Review - Academia Romana Filiala Timisoara. 2005-11 |
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R. Casanueva, F. Azcondo, C. Brañas, S. Bracho
"Output current sensitivity analysis of the LCpCs resonant inverter. Current source design criteria"
IEEE. The 31st Annual Conference of the Industrial Electronics Society IECON 2005 . 2005-11 |
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C. Brañas, F. Azcondo, R. Casanueva, S. Bracho
"Parallel connection of multiple resonant inverters to drive high-power high-intensity discharge lamps"
IEEE. The 31st Annual Conference of the Industrial Electronics Society IECON 2005 . 2005-11 |
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R. Casanueva, C. Brañas, F. Azcondo, S. Bracho
"Resonant converters: properties and applications for variable loads"
IEEE. The 31st Annual Conference of the Industrial Electronics Society IECON 2005. 2005-11 |
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R. Casanueva, F. Azcondo, C. Brañas, S. Bracho
"Análisis de Sensibilidad de la Intensidad de Salida del Inversor Resonante Paralelo-Serie."
Proc. of the XII Annual Seminar on Automatic Control, Industrial Electronics and Instrumentation (SAAEI 2005), Santander. 2005-09 |
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C. Brañas, F. Azcondo, R. Casanueva, S. Bracho
"Multi-Phase Parallel Resonant Inverters"
Proc. of the XII Annual Seminar on Automatic Control, Industrial Electronics and Instrumentation (SAAEI 2005), Santander. 2005-09 |
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F. Díaz, F. Azcondo, C. Brañas, R. Casanueva
"Control de Balastos Electrónicos desde un Microcontrolador PIC16F628"
Proc. of the XII Annual Seminar on Automatic Control, Industrial Electronics and Instrumentation (SAAEI 2005), Santander. 2005-09 |
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C. Brañas, F. Azcondo, R. Casanueva, S. Bracho
"Multi-Phase Parallel Resonant Inverter Applied to HID Lamp Control"
26th International Exhibition & Conference for Power Electronics, Intelligent Motion, Power Quality, PCIM Europe 2005. Nüremberg, Alemania. 2005-06 |
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F. Azcondo, C. Brañas, R. Casanueva, Dragan Maksimovic
"Approaches to Modeling Converters with Current Programmed Control"
1st Power Electronics Education Workshop, PEEW 2005-PESC05. Recife, Brasil. 2005-06 |
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R. Casanueva, F. Azcondo, C. Brañas, S. Bracho
"Analysis, Design and Experimental Results of a High Frequency Power Supply for Spark Erosion"
IEEE Transactions on Power Electronics. 2005-03 |
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Montu Doshi, Jianjian Bian, Regan Zane, F. Azcondo
"Low Frequency Architecture for Multi-Lamp CCFL Systems with Capacitive Ignition"
IEEE Applied Power Electronics Conference and Exhibition. Austin-Texas. USA. 2005-03 |
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F. Azcondo, S. Bracho, R. Casanueva
"Sistema electrónico de potencia con control digital reconfigurable para máquinas de electroerosión"
Oficina Española de Patentes y Marcas. OEPM . 2005-03 |
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F. Azcondo, C. Brañas, R. Casanueva, S. Bracho
"Power Mode Controlled Power Factor Corrector for Electronics Ballast"
IEEE Transactions on Industrial Electronics Vol. 52 No.1 pp.56-65. 2005-02 |
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R. Casanueva, F. Azcondo, C. Brañas, S. Bracho
"Paralleled LCsCp Resonant Converters for Spark Erosion Applications"
Proc. of the IEEE IAS 39th Annual Meeting (IAS 2004). Seattle. USA.. 2004-10 |
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F. Azcondo, C. Brañas, R. Casanueva, S. Bracho
"Power Fed Electronic Ballast"
Proc. of the IEEE IAS 39th Annual Meeting (IAS 2004) Seattle. USA.. 2004-10 |
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C. Brañas, F. Azcondo, R. Casanueva, S. Bracho
"Phase Control of LCp Resonant Inverters for HID Lamp Ballast Applications"
Proc. of the Annual Seminar on Automatic Control, Industrial Electronics and Automation (SAAEI’04). 2004-09 |
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C. Brañas, R. Casanueva, F. Azcondo, S. Bracho
"Convertidores Resonantes: Propiedades y Aplicaciones para la Alimentación de Cargas Irregulares"
Actas del VI Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE’04). 2004-07 |
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R. Casanueva, F. Azcondo, S. Bracho
"Series-parallel resonant converter for an EDM power supply"
Journal of Materials Processing Technology, 149 (2004) 172-177. 2004-06 |
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C. Brañas, F. Azcondo, R. Casanueva, S. Bracho
"Phase Controlled LCpCs Resonant Inverter Applied to HID Lamp Control"
Proceedings of the 2004 IEEE 35th Annual Power Electronics Specialists Conference (PESC’04). pp. 2434-2440. 2004-06 |
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R. Casanueva, F. Azcondo, S. Bracho
"Series-parallel resonant converter for an EDM power supply"
14th International Symposium on Electromachining (ISEM XIV), Edinburgh (UK). 2004-03 |
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C. Brañas, F. Azcondo, S. Bracho
"Study of the Output Power Variation due to Component Tolerances in LCC. Resonant Inverters Applied to HPS Lamps Control"
IEEE Trans. on Industrial Electronics. 2004-02 |
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R. Casanueva, F. Azcondo, S. Bracho
"HF Resonant Power Supply for an Electrical Discharge Machining Impulse Generator"
10th European Conference on Power Electronics and Applications (EPE 2003), Toulouse (France). 2003-09 |
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C. Brañas, F. Azcondo, S. Bracho
"Design of a Resonant Power Source to Drive HPS Lamps"
10th European Conference on Power Electronics and Applications. EPE 2003. 2003-09 |
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C. Brañas, F. Azcondo, S. Bracho
"Low Cost LCp Resonant Inverter as a Power Source fo HPS Lamp Ballast Applications"
24th International conference on Power Electronics, Power Quality and Intelligent Motion (PCIM 2003). Nuremberg (Germany). 2003-05 |
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C. Brañas, F. Azcondo, S. Bracho
"Design of LCpCs Resonant Inverters as a Power Source for HID Lamp Ballast Applications"
18th Annual IEEE Applied Power Electronics Conference and Exposition. (APEC 2003). Miami Beach (FL), USA. 2003-02 |
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C. Brañas, F. Azcondo, S. Bracho
"Experimental study of HPS lamp ignition by using LC network resonance"
The 28th Annual Conference of IEEE Industrial Electronics Society (IECON’02). Sevilla. 2002-11 |
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C. Brañas, F. Azcondo, S. Bracho
"Evaluation of an Electronic Ballast Circuit for HID Lamps with Passive Power Factor Correction"
The 28th Annual Conference of IEEE Industrial Electronics Society (IECON’02). Sevilla. 2002-11 |
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R. Casanueva, Luis A. Chiquito, F. Azcondo, S. Bracho
"Electrical Discharge Machining Experiences with a Resonant Power Supply"
The 28th Annual Conference of IEEE Industrial Electronics Society (IECON’02). Sevilla. 2002-11 |
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R. Casanueva, Luis A. Chiquito, F. Azcondo, S. Bracho
"A control strategy for EDM with a novel power supply"
XVII Conference on Design of Circuits and Integrated Systems (DCIS 2002). Santander. 2002-11 |
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C. Brañas, F. Azcondo, S. Bracho
"Analysis of Tolerances in LCpCs Resonant Inverters Applied to HPS Lamp Control"
XVII Conference on Design of Circuits and Integrated Systems (DCIS 2002). Santander. 2002-11 |
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R. Casanueva, F. Azcondo, S. Bracho
"Control digital específico para un nuevo sistema de electroerosión de tamaño reducido"
Seminario Anual de Automática, Electrónica Industrial e Instrumentación (SAAEI’2002), Alcalá de Henares. 2002-09 |
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R. Casanueva, Luis A. Chiquito, F. Azcondo, S. Bracho
"Current Source LCC Resonant Converter for an EDM Power Supply"
The 27th Annual Conference of IEEE Industrial Electronics Society, IECON01. Denver, CO (USA). 2001-12 |
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C. Brañas, F. Azcondo, S. Bracho
"Study of Output Power Variation due to Component Tolerances in LCsCp Resonant Inverters Applied to HPS Lamp Control"
The 27th Annual Conference of IEEE Industrial Electronics Society, IECON01. Denver, CO (USA). 2001-12 |
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C. Brañas, F. Azcondo, S. Bracho
"Evaluation of an Electronic Ballast Circuit for HID Lamps with Passive Power Factor Correction"
16th Design of Circuits and Integrated Systems Conference, DCIS 2001. Oporto (Portugal). 2001-11 |
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R. Casanueva, C. Brañas, F. Azcondo, S. Bracho
"Optimization of the generation and control of the electric arc in electrical discharge machining processes and in high power discharge lamps"
1st Workshop of the Industry Application Society - IEEE Spanish Chapter. Madrid. 2001-09 |
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R. Casanueva, M. Ochoa, F. Azcondo, S. Bracho
"Current Mode Controlled LCC Resonant Converter for Electrical Discharge Machining Applications"
The 2000 IEEE International Symposium on Industrial Electronics, ISIE2000, Puebla (Mexico), Vol. 2 pg. 505-510. 2000-12 |
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C. Brañas, F. Azcondo, S. Bracho
"Class D LCsCp Series-Parallel Resonant Inverter with Inherent Maximum Output Power Suitable for driving HPS Lamps"
The 2000 IEEE International Symposium on Industrial Electronics, ISIE 2000. Puebla (Mexico). 2000-12 |
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R. Casanueva, M. Ochoa, F. Azcondo, S. Bracho
"Contribution To EDM Based On Power Resonant Converters"
15th Design of Circuits and Integrated Circuit Conference, DCIS2000, Montpellier (Francia), pg. 726-731. 2000-11 |
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C. Brañas, F. Azcondo, S. Bracho
"HPS Lamp Ignition Using Resonance of LC Networks and Considering the Aging Effect"
15th Design of Circuits and Integrated Systems Conference (DCIS 2000). Montpellier (Francia). 2000-11 |
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C. Brañas, F. Azcondo, S. Bracho
"Electronic Ballast for High Pressure Sodium Lamps Based on the Class D Series-Parallel Resonant Inverter with Soft Start-up and Compensated Output Power"
XIV Design of Circuits and Integrated Systems Conference.. 1999-11 |
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C. Brañas, F. Azcondo, S. Bracho
"Electronic Ballast for 250W HPS Lamps Based on the LCC Resonant Inverter with Soft Start-up and Quasi-optimum Control"
Proceedings of the IEEE International Symposium on Industrial Electronics. ISIE 99. 1999-07 |
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C. Brañas, F. Azcondo, S. Bracho
"Electronic ballast for 150W HPS lamps with compensated output power"
Electronics Letters, Vol. 35, No. 13. 1999-06 |
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C. Diez, F. Azcondo, M. Allende
"Sub-optimal PWM Control Integrated Circuit for Induction Motor Drives"
XIII Design of Circuits and Integrated Systems Conference (DCIS98). Madrid. 1998-11 |
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C. Brañas, F. Azcondo, S. Bracho
"Design of an Integrated Circuit for the Control of an Electronic Ballast Loaded by a 150 W High Pressure Sodium Discharge Lamp"
XIII Design of Circuits and Integrated Systems Conference (DCIS98). Madrid. 1998-11 |
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C. Brañas, F. Azcondo, S. Bracho
"Electronic Ballast for HPS Lamps with Power Control by Variation of the Switching Frequency. Soft start-up Method for HPS and Fluorescent Lamps"
24th Annual Conference of the IEEE Industrial Electronics Society (IECON98). Aachen (Germany). 1998-08 |
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C. Brañas, F. Azcondo, S. Bracho
"PWM Control of an Electronic Ballast for a High Pressure Na Lamp in Comparison to Fluorescent Lamps"
24th Annual Conference of the IEEE Industrial Electronics Society (IECON98). Aachen (Germany). 1998-08 |
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C. Brañas, F. Azcondo, S. Bracho
"PWM-Controlled Electronic Ballast for Dimming Control of Fluorescent Lamps"
IEEE International Symposium on Industrial Electronics (ISIE97). Guimaraes (Portugal). 1997-07 |
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Ana M. Díez, Luis M. Díez, F. Azcondo, S. Bracho
"Digital Image Processing for Edge Detection and Pattern Recognition"
IEEE International Symposium on Industrial Electronics (ISIE97). Guimaraes (Portugal). 1997-07 |
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R. Casanueva, F. Porres, F. Azcondo
"Diseño de un Circuito Integrado para el Control de Maniobras de Ascensores"
XI Conference Design of Integrated Circuits and Systems (DCIS96). Sitges (Barcelona). 1996-11 |
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R. Casanueva, F. Porres, F. Azcondo
"Flexible Control for Elevator Systems. ASIC Implementation Criteria"
22nd Annual International Conference of the IEEE Industrial Electronics Society (IECON96). Taipei, Taiwan. 1996-08 |
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F. Azcondo, Julia C. Blanco, Juan Peire
"New Digital Compensation Technique for the Design of a Microcomputer Compensated Crystal Oscillator"
IEEE Transactions on Industrial Electronics, Vol. 42, No. 3. 1995-06 |
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| Diseño y verificación de sistemas electrónicos para comunicaciones |
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Artur Wegele, P. Peñil, E. Villar, Wolfgang Mueller, Da He, Fabian Mischkalla, et. al.
"Updated frameworks"
Deliverable D4.5 the FP7-216807 SATURN Project. 2010-12 |
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J. Pérez, V. Fernández
"3GPP2/802.20 RC/QC-LDPC Encoding"
IEEE European Wireless 2010, Lucca, Italy. 2010-04 |
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J. Pérez, V. Fernández
"Codificador ldpc e interleaver para dvb-s2"
Oficina Española de Patentes y Marcas. OEPM . 2009-09 |
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J. Pérez, V. Fernández
"Reducing the error floor using a two-level permutation in structured eIRA LDPCs"
XIX Conference on Design of Circuits and Integrated Systems (DCIS2008), Grenoble, France. 2008-11 |
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J. Pérez, V. Fernández
"Low-Cost Enconding of IEEE 802.11n"
IET Electronics Letters
Volume 44, Issue 4, pp. 307-308. 14 Feb 2008. 2008-03 |
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J. Pérez, K. Andrews
"Low-Density Parity-Check Code Design Techniques to Simplify Encoding"
The Interplanetary Network Progress Report, Volume 42-171, Jet Propulsion Laboratory (NASA), California Institute of Technology, Pasadena, California. 2007-11 |
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J. Pérez, V. Fernández
"Improved Architectures for VLC MAP decoders"
IEEE International Symposium on Wireless Communication Systems (ISWCS), Valencia, Spain. 2006-09 |
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J. Pérez, V. Fernández, Fernando Vallejo, Ana Jalón
"Novel DVB-S2 FEC Encoder Architecture"
9th International Workshop on Signal Processing for Space Communications. ESTEC, Noordwijk, The Netherlands. 2006-09 |
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J. Pérez, V. Fernández
"Hierarchical and Pseudo-Random eIRA Codes Based on BIBDs and Primitive Interleavers"
IEEE International Conference on Wireless Information Networks and Systems, Setubal, Portugal. 2006-08 |
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J. Pérez, V. Fernández
"Near Random Performance of Structured eIRA Codes"
IEEE and IEE co-sponsored Signal Processing for Wireless Communications (SPWC) Workshop, London. 2006-05 |
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J. Pérez, V. Fernández
"Hardware Aware eIRA LDPC Code Generation"
IEEE International Symposium of Wireless Communication Systems 2005(ISWCS 2005), Siena, Italy. 2005-09 |
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J. Pérez, V. Fernández
"Optimizations in max-log-map LLRe VLSI architecture"
IEEE International Symposium on Signals, Circuits and Systems (ISSCS). Iasi (Romania)
. 2005-07 |
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J. Pérez, V. Fernández
"Optimizations in DVB-RCS Turbo Decoder Based on Trellis Structure"
XIX Conference on Design of Circuits and Integrated Systems (DCIS2004). Bordeaux. 2004-09 |
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J. Pérez, V. Fernández, H. Posadas, V. Fernández
"Estudio de viabilidad de DVB-S2 en Banda Ka"
Memoria técnica justificativa del proyecto PROFIT PNE-001/2003-EMP. 2004-04 |
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J. Pérez, P. Sánchez, V. Fernández
"FGPA Implementation of a MAP Decoder for DVB-S Satellite Reception"
XVIII Conference on Design of Circuits and Integrated Systems (DCIS2003). Ciudad Real. 2003-11 |
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V. Fernández, A. Jalón, L. Berrojo, Yves Leroy
"Design, Functional Verification and Test of a MPEG2-TS Multiplexer for an On-Board Satellite Processor"
XVII Conference on Design of Circuits and Integrated Systems (DCIS 2002). Santander. 2002-11 |
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J. Pérez, P. Sánchez
"FPGA implementation of DVB-RCS turbo coder and decoder"
Proceedings of the XVII Design of Circuits and Integrated Systems Conference, Servicio de Publicaciones de la Universidad de Cantabria. 2002-11 |
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V. Fernández, L. Berrojo, J. Prat, Y. Leroy
"Verification of a Digital Video Broadcasting Satellite System"
16th Design of Circuits and Integrated Systems Conference, DCIS 2001. Oporto (Portugal). 2001-11 |
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L. Chen, S. Dey, P. Sánchez, K. Sekar, Y.H. Chen
"Embedded Hardware and Software Self-Testing Methodologies for Processor Cores"
37th Design Automation Conference, Los Angeles, California. 2000-06 |
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A. Antón, E. Villar, D.B. de Vries & S.M. H. de Groot
"Design and functional description of a sender and receiver for ATM adaptation layer protocols"
XIII Design of Circuits and Integrated Systems Conference (DCIS98). Madrid. 1998-11 |
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Ll. Terés, Y. Torroja, S. Olcoz, E. Villar
"VHDL: Lenguaje estándar de Diseño Electrónico"
McGraw Hill. 1998-01 |
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 |
E. Villar, P. Sánchez
"Síntesis"
VHDL: Lenguaje estándar de diseño electrónico
McGraw-Hill. 1998-01 |
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A. Antón, E. Villar, D.B. de Vries, S. M. H. de Groot.
"Flexible architecture for processing ATM adaptation layer protocols (AAL1-5)"
IEEE Journal of Electrical Engineering, V.49, N.3-4, pp. 70-75. 1998-01 |
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P. Tabuenca, E. Villar
"An algorithm for clock cycle selection in behavioral synthesis"
Journal of Systems Architecture, V.44, N.9-10, North-Holland, pp. 773-786. 1998-01 |
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A. Antón, E. Villar, D. B. de Vries, S.M. Heemstra de Groot
"Design and functional description of a receiver for ATM Adaptation Layer Protocols"
6th HCM BELDESIGN Workshop. Aveiro (Portugal). 1997-10 |
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A. Antón, E. Villar, S.M. Heemstra de Groot, D. B. de Vries
"Flexible Architecture for Processing ATM Adaptation Layer Protocols (AAL1-5)"
First Electronic Circuits and Systems Conference (ECS97). Bratislava (Slovakia). 1997-09 |
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J. L. Barreda, P. Sánchez
"Current fault modeling in VITAL"
XI Conference Design of Integrated Circuits and Systems (DCIS´96). Sitges (Barcelona).. 1996-11 |
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H.W.A. Teunissen, D. B. de Vries, S.M. Heemstra de Groot, A. Antón, E. Villar
"Design of a Flexible Architecture for Processing ATM Adaptation Layer Protocols"
ProRISC/IEEE Workshop on Circuits, Systems and Signal Processing. Mierlo (The Netherlands). 1996-11 |
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H.W.A. Teunissen, D. B. de Vries, S.M. Heemstra de Groot, A. Antón, E. Villar
"A Flexible Architecture for Processing ATM Adaptation Layer Protocols"
4th HCM BELSIGN Workshop, Santander. 1996-10 |
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J. L. Barreda, P. Sánchez
"Current modeling in VITAL"
ATW Workshop. 1996-06 |
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M. Imai, E. Villar
"ASPDAC 1995: HDL synthesizability and interoperability"
IEEE Design & Test of Computers. Panel Summaries, pp 3-4. 1996-04 |
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W. Ecker, E. Villar
"VHDL multi-wait descriptions for synthesis"
Working Conference of VHDL Forum for CAD in Europe, Dresden Germany, pp 59-69. 1996-04 |
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H.W.A. Teunissen, D.B. de Vries, S.M. Heemstra de Groot, A. Antón, E. Villar
"Design of a flexible architecture for processing ATM adaptation layer protocols"
CTIT Technical Report series, N. 96-40 University of Twente, The Netherlands. 1996-01 |
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M. Selz, W. Ecker, E. Villar
"VHDL synthesis description portability: The need for Level-x synthesis subsets"
Journal of System Architecture 42, North-Holland, pp 105-116. 1996-01 |
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E. Villar
"The Level-0 VHDL Synthesis Syntax and Semantics - 2nd Part"
The VHDL Newsletter, No. 20, pp.1 and 12. 1995-12 |
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COMITE PRENDA
"Importancia de una metodología para las nuevas técnicas de diseño de ASICs"
X Congreso de Diseño de Circuitos Integrados y Sistemas (DCIS95). Zaragoza. 1995-11 |
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E. Villar
"The Level-0 VHDL Synthesis Syntax and Semantics - 1st Part"
The VHDL Newsletter, No. 19, pp. 10-11. 1995-10 |
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J. L. Barreda, I. Hidalgo, V. Fernández, P. Sánchez, E. Villar
"Fault Modeling in VITAL"
Proceedings of the Workshop on Libraries, Component Modeling, and Quality Assurance. Nantes, France. 1995-04 |
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M. Selz, W. Ecker, E. Villar
"VHDL synthesis description portability: The need for Level-x Synthesis Subsets"
Spring´95 Working Conference of the VHDL Forum for CAD in Europe. Nantes (France). 1995-04 |
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Pedro Tabuenca, E. Villar, L. Muñoz, R. Sanz
"Estudio de viabilidad de la implementación ASIC"
Documento Final del proyecto GAME "Análisis de viabilidad de un ASIC para chasis de baja". 1995-03 |
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Comité PRENDA
"Metodología para el diseño de ASICs"
Documento Entregable PRENDA/ENT/T14-01/CON del proyecto GAME PRENDA. 1995-02 |
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 |
C. Delgado Kloos, E. Villar
"VHDL: El lenguaje estándar de diseño electrónico"
Novática. 1995-01 |
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Comité PRENDA
"Guia de referencia general de la metodología"
Documento entregable del proyecto GAME PRENDA. 1994-10 |
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Comité PRENDA
"Proyecto para la especificación y normalización en el diseño de ASICs (PRENDA)"
III Jornadas Técnicas de Calidad en Tecnologías Electrónicas, T.I+D, Madrid. 1994-10 |
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| Métodos de test de circuitos integrados digitales y mixtos |
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J. Miguel, David Rivas, Y. Lechuga, M. Allende, M. Martínez
"A novel computer-assisted design tool for implantable MEMS pressure sensors"
Microprocessors and Microsystems. Eselvier. Aceptada |
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J. Miguel, David Rivas, M. Allende, Y. Lechuga, M. Martínez
"Low-Power Analog Front-End for Intelligent Stents"
XXX CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (DCIS 2015). 2015-11 |
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David Rivas, J. Miguel, Y. Lechuga, M. Allende, M. Martínez
"CMD, AN AUTOMATED DESIGN TOOL FOR BLOOD PRESSURE SENSING CAPACITIVE MEMS"
Proceedings of the 26th micromechanics and microsystems Europe Workshop. 2015-09 |
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J. Miguel, David Rivas, M. Allende, Y. Lechuga, M. Martínez
"Implantable MEMS Pressure Sensors Modelling Tool"
Proceedings of the Euromicro Conference
on Digital System Design (DSD2015). 2015-08 |
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David Rivas, J. Miguel, Y. Lechuga, M. Allende, M. Martínez
"Energy-Efficient Implantable Transmitter for Restenosis
Monitoring with Intelligent-Stents"
37th Annual International Conference of IEEE Engineering in Medicine and Biology Society (EMBC 2015). 2015-08 |
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J. Miguel, David Rivas, Y. Lechuga, M. Allende, M. Martínez
"Oscillation-based Approach Applied to a Low-Power
Analog Front-End for an Implantable Cardiac Device"
Proceedings of the 20th International Mixed-Signal Testing Workshop (IMSTW 2015). 2015-08 |
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J. Miguel, David Rivas, M. Allende, Y. Lechuga, M. Martínez
"Pressure-based intelligent stent for restenosis control"
2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME 2015). 2015-06 |
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J. Miguel, Y. Lechuga, M. Martínez, Jose R. Berrazueta
"Fault Modeling of Implantable MEMS sensors"
Proceedings of the International Conference on Biomedical Electronics and Devices. BIODEVICES 2015. 2015-01 |
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J. Miguel, Y. Lechuga, M. Martínez
"A MEMS Design Tool for Blood-Pressure Sensing"
Proceedings of the Conference on Design of Circuits and Integrated Circuits (DCIS 2014). 2014-11 |
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J. Miguel, Y. Lechuga, M. Martínez
"CMD, an automated design program for blood pressure sensing capacitive MEMS"
11th International Conference on Nanosciences & Nanotechnologies (NN14). 2014-07 |
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J. Miguel, Y. Lechuga, M. Martínez, S. Bracho
"Modeling of Faulty Implantable MEMS Pressure
Sensors"
Proceedings of the 26th International Conference on Microelectronics (ICM 2014). 2014-05 |
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J. Miguel, Y. Lechuga, R. Mozuelos, M. Martínez
"Fault injection in an implantable MEMS-based pressure sensing device"
Proceedings of the 28th Design of Circuits and Integrated Systems Conference (DCIS 2013). 2013-11 |
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R. Mozuelos, Y. Lechuga, M. Martínez, S. Bracho
"Behavioral model of folded and interpolated ADCs for test evaluation—Case study: Structural DfT method"
Microelectronics Journal, Volume 44, Issue 5, May 2013, Pages 382–392. 2013-05 |
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J. Miguel, Y. Lechuga, R. Mozuelos, M. Martínez
"Implantable Sensor System for Remote Detection
of a Restenosis Condition"
4th Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS 2013). 2013-04 |
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J. Miguel, Y. Lechuga, R. Mozuelos, M. Martínez
"Modeling of an implantable device for remote arterial pressure
measurement"
SPIE Microtechnologies 2013. 2013-04 |
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J. Miguel, Y. Lechuga, M. Martínez
"Analysis of Fault Injection in Implantable Capacitive Blood-Pressure Sensors"
International Conference on Biomedical Electronics and Devices (Biodevices 2013). 2013-02 |
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J. Miguel, R. Mozuelos, M. Martínez
"Modelling an implantable sensor system for restenosis monitorization in the pulmonary artery"
XXVII Conference on Design of Circuits and Integrated Systems (DCIS12)
. 2012-11 |
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J. Miguel, R. Mozuelos, M. Martínez
"Behavioural Analysis of an Implantable Flow and Pressure Sensing Device"
International Conference on Biomedical Electronics and Devices (Biodevices 2012). 2012-02 |
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R. Mozuelos, Y. Lechuga, M. Martínez, S. Bracho
"Structural Test Approach for Embedded Analog Circuits based on a Built-In Current Sensor"
Journal of Electronic Testing (Springer). 2011-04 |
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Y. Lechuga, R. Mozuelos, M. Martínez, S. Bracho
"Fault Evaluation of a Distributed Preamplifying Stage of a High-Speed Folded ADC"
XXV Conference on Design of Circuits and Integrated Systems, DCIS'10. 2010-11 |
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R. Mozuelos, Y. Lechuga, M. Martínez, S. Bracho
"Test of Embedded Analog Circuits based on a Built-In Current Sensor"
European Test Symposium 2010, ETS10. 2010-05 |
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R. Mozuelos, Y. Lechuga, M. Martínez, S. Bracho
"Test based on Built-In Current Sensors for Mixed-Signal Circuits"
Emerging Trends in Technological Innovation, IFIP AICT 314, Springer. 2010-02 |
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Y. Lechuga, R. Mozuelos, M. Martínez, S. Bracho
"Structural DfT Strategy for High-speed ADCs"
Emerging Trends in Technological Innovation, IFIP AICT 314, Springer*. 2010-02 |
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 |
Y. Lechuga
"Métodos de Test Estructural Aplicados a Circuitos Mixtos de Altas Prestaciones"
Universidad de Cantabria. 2009-09 |
|
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R. Mozuelos
"Test Basado en Sensores de Corriente Internos para Circuitos Integrados Mixtos (Analógicos-Digitales)"
Universidad de Cantabria. 2009-09 |
|
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Y. Lechuga, R. Mozuelos, M. Martínez, S. Bracho
"Optimization of a Structural DfT Targeting Fault Detection on High‐Speed ADCs"
European Test Symposium (ETS'09). Sevilla(E). 2009-05 |
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Y. Lechuga, Ahcène Bounceur, R. Mozuelos, M. Martínez, S. Bracho, Salvador Mir
"Test Limit Evaluation for an ADC Structural Design-for-Test Approach by using a CAT Platform"
Proceedings of the Conference on Design of Circuits and Integrated Systems DCIS 2008, Grenoble (Francia). 2008-11 |
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R. Mozuelos, Y. Lechuga, M. Martínez, S. Bracho
"Structural DfT Approach on Folded ADCs"
14th IEEE International Conference on Electronics, Circuits and Systems(ICECS'2007). Marrakech(Marruecos). 2007-12 |
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R. Mozuelos, Y. Lechuga, M. Martínez, S. Bracho
"DfT Behavioural Description for Folded ADCs"
12th IEEE International Mixed-Signals Testing Workshop (IMSTW´06)
Edinburgh(UK). 2006-06 |
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Y. Lechuga, R. Mozuelos, M. Allende, M. Martínez, S. Bracho
"Fault detection in switched current circuits using built-in transient current sensors"
Journal of Electronic Testing-Theory and Applications 21 (6): 583-598. 2005-12 |
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R. Mozuelos, Y. Lechuga, M. Martínez, S. Bracho
"Test of a Switched Capacitor ADC by a Built-In Charge Sensor"
Microelectronics Journal 36 (12): 1064-1072. 2005-11 |
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Y. Lechuga, R. Mozuelos, M. Martínez, S. Bracho
"Design for Test of High-Speed Folded ADCs"
XX Conference on
Design of Circuits and Integrated Systems(DCIS 2005) Lisboa(P). 2005-11 |
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Y. Lechuga, R. Mozuelos, M. Martínez, S. Bracho
"Test de Preamplificadores en Convertidores A/D Doblados"
Proc. of the XII Annual Seminar on Automatic Control, Industrial Electronics and Instrumentation (SAAEI 2005), Santander. 2005-09 |
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R. Mozuelos, Y. Lechuga, M. Martínez, S. Bracho
"Test of Averaged Preamplifiers in Folded ADCs "
11th IEEE International Mixed-Signals Testing Workshop (IMSTW 2005) Cannes(F). 2005-06 |
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R. Mozuelos, Y. Lechuga, M. Allende, M. Martínez, S. Bracho
"Experimental Evaluation of a Built-in Current Sensor for Analog Circuits"
XIX Conference on Design of Circuits and Integrated Systems (DCIS2004). Bordeaux (France). 2004-11 |
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Y. Lechuga, R. Mozuelos, M. Allende, M. Martínez, S. Bracho
"Experimental Analysis of Transient Current Test Based on dIDD Variations in S2I Memory Cells"
XIX Conference on Design of Circuits and Integrated Systems (DCIS2004). Bordeaux (France). 2004-11 |
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R. Mozuelos, Y. Lechuga, M. Martínez, S. Bracho
"Characterization of an SC ADC by a Built-In Charge Sensor"
10th International Mixed-Signal Testing Workshop (IMSTW2004). Portland (USA). 2004-06 |
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Y. Lechuga, R. Mozuelos, M. Martínez, S. Bracho
"Dynamic Current Testing Strategies for S2I Algorithmic A/D Converters"
XVIII Conference on Design of Circuits and Integrated Systems (DCIS2003). Ciudad Real (Spain). 2003-11 |
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R. Mozuelos, Y. Lechuga, M. Martínez, S. Bracho
"SC Algorithmic ADC Test with a Built-In Charge Sensor"
XVIII Conference on Design of Circuits and Integrated Systems (DCIS2003). Ciudad Real (Spain). 2003-11 |
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Y. Lechuga, R. Mozuelos, M. Martínez, S. Bracho
"Test generation in algorithmic switched current ADCs"
9th International Mixed-Signal Testing Workshop (IMSTW2003). Sevilla. 2003-06 |
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Y. Lechuga, R. Mozuelos, M. Martínez, S. Bracho
"Built-In Sensor Based on Current Supply High-Frequency Behaviour"
Electronic Letters, Vol 39, No. 9. 2003-05 |
|
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Y. Lechuga, M. Martínez, S. Bracho
"Fault Detection in Algorithmic ADC Monitoring Charge in SC Converters and Dynamic Current in SI Converters"
IX Workshop IBERCHIP (IWS´2003). La Habana (Cuba). 2003-03 |
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Y. Lechuga, R. Mozuelos, M. Martínez, S. Bracho
"Fault detection in algorithmic switched-current ADC using built-in sensors"
XVII Conference on Design of Circuits and Integrated Systems (DCIS 2002). Santander. 2002-11 |
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Y. Lechuga, R. Mozuelos, M. Martínez, S. Bracho
"Built-in Dynamic Current Sensor for Hard-to-Detect Faults in Mixed-Signal ICs"
Design, Automation and Test in Europe, DATE 2002. Paris (France). 2002-03 |
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Y. Lechuga, R. Mozuelos, M. Martínez, S. Bracho
"Hard-to-Detect Faults by Dynamic Current Sensor in Analogue Circuits"
3rd IEEE Latin-American Test Workshop, LATW2002. Montevideo (Uruguay). 2002-02 |
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R. Mozuelos, M. Martínez, S. Bracho
"Built-In Sensor Based on the Time-Variation of the Transient Current Supply in Analogue Circuits"
16th Design of Circuits and Integrated Systems Conference, DCIS 2001. Oporto (Portugal). 2001-11 |
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Y. Lechuga, M. Martínez, S. Bracho
"Dynamic Current Test of Switched-current Building-blocks"
15th Design of Circuits and Integrated Systems Conference (DCIS 2000). Montpellier (Francia). 2000-11 |
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R. Mozuelos, M. Martínez, S. Bracho
"Catastrophic and Parametric Fault Detection By a Transient Current Test"
XIV Design of Circuits and Integrated Systems Conference.. 1999-11 |
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L. González, D. Pando, M. Martínez, S. Bracho
"Dynamic Current Test of Switched-current Buildings-blocks"
IEEE International Mixed Signal test Symposium. Vancouver (Canada). 1999-06 |
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M. J. López, M. Martínez, S. Bracho
"A Method for designing a Deterministic Test Pattern Generator based on Cellular Automata"
Journal of Electronic Testing: Theory and Applications. 1999-06 |
|
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L. González, M. Martínez, S. Bracho
"Fault Detection in Switched-current Building-blocks by Dynamic Current Test"
XIII Design of Circuits and Integrated Systems Conference (DCIS98). Madrid. 1998-11 |
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J. Argüelles, M. J. López
"Chances of Supply Current Test Techniques for Mixed Signal Integrated Circuits"
IEE Systems on a Chip, UCD (Dublín). 1998-09 |
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R. Mozuelos, M. Martínez, S. Bracho
"Dynamic Power Supply Current Measurements for Catastrophic and Parametric Fault Detection"
4th International Mixed Signal Testing Workshop (IMSTW98). The Hague (The Netherlands). 1998-06 |
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J. Argüelles, M. J. López
"Reliability analysis for a power-supply current test"
IEEE European Test Workshop. Barcelona. 1998-05 |
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R. Mozuelos, M. Martínez, S. Bracho
"Sensor Performances in Dynamic Power Supply Current Test"
IEEE Hot Topic Workshop on Current Testing for Analogue and Mixed Signal Devices (CTAMS98). Paris (Francia). 1998-02 |
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M. J. López, S. Bracho
"Cellular Automata-based Mixed Test Pattern Generator for Built-in Self-Test"
XII Design of Circuits and Integrated Systems Conference (DCIS97). Sevilla. 1997-11 |
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J. Argüelles, S. Bracho
"A Design for Test Proposal for Improving Dynamic Current Testing Reliability on Regenerative Sense Amplifiers"
IEEE International Workshop on IDDQ Testing. Washington, DC (USA). 1997-11 |
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J. Argüelles, M. J. López
"A Novel Built-in Dynamic Supply Current Monitor for Mixed IC Testing"
IEE Colloquium on Testing Mixed Signal Circuits and Systems. London (England). 1997-10 |
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S. Bracho, M. Martínez
"Catastrophic and Parametric Fault Detection by Dinamic Power Supply Current Test"
IEE Colloquium on Testing Mixed Signal Circuits and Systems. London (England). 1997-10 |
|
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|
|
M. J. López, S. Bracho
"Cellular Automata-based Mixed Test Pattern Generator for Built-in Self-test"
IEEE European Test Workshop (ETW97). Cagliari (Italia). 1997-05 |
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S. Bracho
"Dynamic Current Testing Methods in Mixed Signal Integrated Circuits"
Open Workshop AMATIST Project & Final Review Meeting. University of Twente (NL). 1997-05 |
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T. Olbrich, R. Mozuelos, A. Richardson, S. Bracho
"Design for Test (DfT) study on a current mode DAC"
IEE Circuits, Devices and Systems. Volume 143, Number 6, pp 374-379. 1996-12 |
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J. Argüelles, S. Bracho
"Signature Analysis for Fault Detection of Mixed-Signal ICs Based on Dynamic Power-Supply current"
Journal of Electronics Testing (Special issue on Analog and Mixed Signal Testing), Vol. 9, Nº. 1/2. 1996-08 |
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M. J. López, M. Martínez, S. Bracho
"A Method to calculate a Deterministic Test Pattern Generator based on Cellular Automata"
IEEE European Test Workshop, Montpellier (F). 1996-06 |
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|
V. Puente, M. Martínez, S. Bracho
"Analog Circuit Test Based in Hypothesis Test of Dynamic Current Consumption"
International Mixed Signal Testing Workshop. Canada. 1996-05 |
|
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|
|
I. Hidalgo, P. Sánchez
"System Level Fault Simulation"
BELSIGN Workshop. Corcega. 1996-04 |
|
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|
|
J. L. Barreda, P. Sánchez, E. Villar
"Current fault modeling in VITAL"
VHDL International User´s Forum. Santa Clara, CA, USA. 1996-02 |
|
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|
|
I. González, E. Villar, S. Bracho
"Inserción automática de estructuras BIST en entornos de síntesis usando VHDL"
X Congreso de Diseño de Circuitos Integrados y Sistemas (DCIS95). Zaragoza. 1995-11 |
|
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|
|
I. Hidalgo, P. Sánchez
"Técnica para simulación de fallos en un entorno VHDL"
Congreso de Diseño de Circuitos Integrados y Sistemas (DCIS95). Zaragoza. 1995-11 |
|
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|
|
R. Mozuelos, J. Argüelles, M. Martínez, S. Bracho
"Test basado en Iddt de un convertidor digital-analógico"
Congreso de Diseño de Circuitos Integrados y Sistemas (DCIS95). Zaragoza. 1995-11 |
|
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|
M. J. López, M. Martínez, S. Bracho
"Generador de vectores de test determinista basado en autómatas celulares: un método del cálculo de sus reglas"
Congreso de Diseño de Circuitos Integrados y Sistemas (DCIS95). Zaragoza. 1995-11 |
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|
V. Puente, M. Martínez, S. Bracho
"Test de Hipótesis basado en el consumo dinámico de intensidad"
X Congreso de Diseño de Circuitos Integrados y Sistemas (DCIS95). Zaragoza. 1995-11 |
|
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|
V. Fernández, P. Sánchez
"Síntesis de alto nivel para scan parcial"
Actas del Congreso de Diseño de Circuitos Integrados y Sistemas. Zaragoza. 1995-11 |
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|
M. Martínez, S. Bracho
"Weighted BIST Structures in the Aritmetic Unit of a Communication Processor"
IEE Proceedings-E, Computers and Digital Techniques, Vol. 142, No. 5. 1995-09 |
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M. Martínez, S. Bracho
"Métodos de Test de Intensidad en Circuitos Mixtos"
Seminario Anual de Automática y Electrónica Industrial. Tarragona. 1995-09 |
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M. Martínez, S. Bracho
"Test Methodologies in Mixed Signal Testing"
37th Midwest Symposium on Circuit and Systems. Rio (Brasil). 1995-08 |
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M. Allende, F. J. Llacer, M. Martínez, S. Bracho
"Partial Scan Insertion Tool for Highly Sequential Digital Circuits"
1st IEEE International on-line Testing Workshop. Nice (F). 1995-07 |
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J. Argüelles, M. Martínez, S. Bracho
"Signature Analysis in a Dynamic Current Test of Mixed-signals ICs"
International Mixed Signal Testing Workshop. Grenoble (F). 1995-06 |
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J. Argüelles, M. J. López, J. Blanco, M. Martínez, S. Bracho
"Iddt testing of continuos-time filters"
13th VLSI Test Symposium. Princeton (USA). 1995-04 |
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M. J. López, M. Martínez, J. Argüelles, S. Bracho
"Deterministic Test Pattern Generation based on Cellular Automata"
2nd Archimedes Open Workshop on Synthesis of Testable Circuits. Barcelona. 1995-02 |
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| Diseño y verificación de sistemas embebidos HW/SW |
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E. Villar, J. Merino, H. Posadas, R. Henia (Thales TRT), L. Rioux (Thales TRT)
"Mega-Modeling of complex, distributed, heterogeneous CPS systems"
Microprocessors and Microsystems (accepted). 2020-08 |
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E. Villar
"Megamodeling of complex, distributed, heterogeneous CPS systems"
Summer School on Cyber-Physical Systems and Internet-of-Things - CPS&IoT’2019, Budva, Montenegro, 2019. 2019-09 |
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Á. Díaz, E. Villar, P. Sánchez
"Integrated Framework for Reusable Multi-Level Embedded System Verification"
Work-in-Progress Session, DAC, San Francisco. 2018-06 |
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E. Villar
"Model-Driven Analysis of Security, Reliability, Test, Privacy, Safety and Trust of IoE Services
"
Surrealist Workshop of the IEEE European Test Symposium, Bremen, Germany. 2018-05 |
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E. Villar
"Model-Driven Analysis and Design of IoT Systems"
DATE Workshop W06: Embedded Software for Industrial IoTs, ESIIT 2018. 2018-03 |
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Á. Díaz, E. Villar, Daniel Peña
"Short and Long Distance Marker Detection Technique in Outdoor and Indoor Environments for Embedded Systems"
XXXI Conference on Design of Circuits and Integrated Systems, DCIS 2017. 2017-11 |
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F. Herrera, J. Medina, E. Villar
"Modeling Hardware/Software Embedded Systems with UML/MARTE: A Single-Source Design approach"
in Soonhoi Ha and Jürgen Teich (Eds): "Handbook of Hardware/Software Codesign", Springer. 2017-09 |
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J. Medina (UC-ISTR), E. Villar
"Towards MARTE++: An Enhanced UML-based Language to Model and Analyse Real-Time and Embedded Systems for the IoT Age"
Forum on Specification and Design Languages, Verona, 2017. 2017-09 |
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H. Hassan, L. T. Yang, J. Xue, E. Villar
"Special issue on: “Heterogeneous architectures for Cyber-physical
systems (HACPS)”"
Microprocessors and Microsystems N.52, Elsevier, pp. 333–334. 2017-07 |
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K. Grüttner, R. Görgen, S. Schreiner, F. Herrera, P. Peñil, J. Medina, E. Villar, et al.
"CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties"
Microprocessors and Microsystems, V.51, pp. 39-55, doi=10.1016/j.micpro.2017.03.012. 2017-06 |
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F. Mallet, E. Villar, F. Herrera
"MARTE for CPS and CPSoS"
in S. Nakajima, J.P. Talpin, M. Toyoshima and H. Yu (Eds.): "Cyber-Physical System Design from an Architecture Analysis Viewpoint: Communications of NII Shonan Meetings", Springer, pp.81-108, doi="10.1007/978-981-10-4436-6. 2017-05 |
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E. Villar, P. Martínez
"Positioning System for Recreated Reality Applications based on high performance Video-Processing"
in A. Molnos, C. Fabre (Eds.):"Model-Implementation Fidelity in Cyber Physical System Design", pp.201-230, Springer. 2016-12 |
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H. Posadas, E. Villar
"Using Professional Resources for Teaching Embedded SW Development"
Revista Iberoamericana de Tecnologias del Aprendizaje, V. 11, I. 4, IEEE, pp. 248 – 255. 2016-11 |
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R. Gorgen, K. Gruttner, F. Herrera, P. Peñil, J. Medina, E. Villar, G. Palermo, W. Fornaciari, C. Brandolese, D. Gadioli, et. al.
"CONTREX: Design of Embedded Mixed-Criticality CONTRol Systems under Consideration of EXtra-Functional Properties "
19th Euromicro Conference on Digital System Design, DSD 2016, IEEE. 2016-09 |
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P. Peñil, H. Posadas, Julio Medina, E. Villar
"UML-Based Single-Source Approach for Evaluation and optimization of Mixed-Critical Embedded Systems
"
XXX Conference on Design of Circuits and Integrated Systems, DCIS 2015, IEEE. 2015-11 |
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E. Villar, P. Martínez, F. Alcalá, P. Sánchez, V. Fernández
"Método y sistema de localización espacial mediante marcadores luminosos para cualquier ambiente"
Oficina Española de Patentes y Marcas, OEPM. 2015-11 |
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A. Quevedo, G. Callico, S. López, R. Sarmiento, A. Nicolás, P. Sánchez, E. Villar
"System Level Methodology based on VIPPE applied to the implementation of a Scalable Video Decoder on the ZynQ platform"
Conference on Design of Circuits and Integrated Systems, DCIS 2015. doi: 10.1109/DCIS.2015.7388604. 2015-11 |
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J. Wan, C-F. Lai, S. Mao, E. Villar
"J. Wan, C-F. Lai, S. Mao and E. Villar: "Editorial: Innovative circuit and system design methodologies for green cyber-physical systems”, "
Microprocessors and Microsystems, V.39, Elsevier, pp. 1231–1233. 2015-11 |
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F. Herrera, P. Peñil, E. Villar
"UML/MARTE Modelling for Design Space
Exploration of Mixed-Criticality Systems on top
of Time-Predictable HW/SW Platforms"
Jornadas de Computación Empotrada (JCE15). 2015-09 |
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P. Peñil, P. Sánchez, David de La Fuente, Jesús Barba, Juan Carlos López, Xerach Peña
"Building a Dynamically Reconfigurable System Through a High-Level Development Flow"
Forum on specification & Design
Languages (FDL 2015). 2015-09 |
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H. Posadas, P. Peñil, A. Nicolás, E. Villar
"Automatic synthesis of communication and concurrency for exploring component-based system implementations considering UML channel semantics"
Journal of System Architecture, V.61, I.8, pp.341–360. 2015-09 |
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F. Herrera, P. Peñil, E. Villar
"A model-based, single-source approach to design-space exploration and synthesis of mixed-criticality systems"
18th International Workshop on Software and Compilers for Embedded Systems, SCoPES 2015, ACM. 2015-06 |
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L. Diaz, E. González, E. Villar, P. Sánchez
"VIPPE: Parallel simulation and performance analysis of complex embedded systems"
HiPPES4CogApp: High Performance, Predictable Embedded Systems for Cognitive Application. 2015-01 |
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H. Posadas, A. Nicolás, P. Peñil, E. Villar, Florian Broekaert, Michel Bourdelles, Albert Cohen, Mihai T. Lazarescu, Luciano Lavagno, Andrei Terechko, Miguel Glassee, Manuel Prieto
"Improving the Design Flow for Parallel and Heterogeneous
Architectures running Real-Time applications: The PHARAON FP7 project"
Microprocessors and Microsystems,V.38, I.8, Part B, pp. 960–975. 2014-11 |
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A. Nicolás, P. Peñil, H. Posadas, E. Villar
"Automatic Deployment Of Component-Based Embedded Systems From UML/MARTE Models Using MCAPI"
XXIX Conference on Design of Circuits and Integrated Systems, DCIS 2014. 2014-11 |
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Javier González Bayón, P. Sánchez, Javier Barreda
"Efficient Implementation of Pattern Matching
Recognition in Heterogeneus Architectures"
XXIX Conference on Design of Circuits and Integrated Systems, DCIS 2014. 2014-11 |
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L. Diaz, E. González, E. Villar, P. Sánchez
"VIPPE, parallel simulation and performance analysis of multi-core embedded systems on multi-core platforms"
XXIX Conference on Design of Circuits and Integrated Systems, DCIS 2014. 2014-11 |
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H. Posadas, P. Peñil, A. Nicolás, E. Villar
"Automatic synthesis of embedded SW for evaluating physical implementation alternatives from UML/MARTE models supporting memory space separation"
Microelectronics Journal, V.45, I.10, pp.1281–1291, doi: 10.1016/j.mejo.2013.11.003. 2014-10 |
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L. Diaz, E. González, E. Villar, P. Sánchez
"VIPPE: Native simulation and performance analysis framework for multi-processing embedded systems"
Proceedings of the JCE-Sarteco 2014. 2014-09 |
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A. Nicolás, P. Peñil, H. Posadas, E. Villar
"Automatic Synthesis over multiple APIs from UML/MARTE Models for easy Platform Mapping and Reuse"
Proceedings of the EuroMicro DSD Conference, IEEE, 2014. 2014-08 |
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L. Diaz, P. Sánchez
"Host-compiled Parallel Simulation of Many-core Embedded Systems"
San Francisco, DAC2014. 2014-06 |
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L. Lavagno (PoliTo), M. Lazarescu (PoliTo), H. Posadas, A. Nicolás, E. Villar
"Parallel and Heterogeneous Architectures for Real-Time Applications"
University Booth, DATE 14, Dresden. 2014-03 |
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F. Herrera, P. Peñil, H. Posadas, E. Villar
"Model-Driven Methodology for the Development of Multi-level Executable Environments"
J. Haase (Ed.): "Models, Methods and Tools for Complex Chip Design", Lecture Notes in Electrical Engineering, V.265, Springer. 2014-01 |
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F. Herrera, H. Posadas, P. Peñil, E. Villar, F. Ferrero (GMV), R. Valencia (GMV), G. Palermo
"The COMPLEX methodology for UML/MARTE modeling and design-space exploration of embedded systems"
Journal of Systems Architecture, V.60, N.1, Elsevier, pp.55–78. 2014-01 |
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E. Ebeid (U.Ver.), F. Fummi (U.Ver.), D. Quaglia (U.Ver.), H. Posadas, E. Villar
"A Framework for Design-Space Exploration and Performance Analysis of Networked Embedded Systems"
Proceedings of the 6th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, ACM. 2014-01 |
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E. Villar, A. Nicolás, P. Peñil, H. Posadas
"Modeling and SW Synthesis for Heterogeneous Embedded Systems in UML/MARTE"
Tutorial SD1: "High-Level Specifications to Cope With Design Complexity" in ASP-DAC 2014, Singapore
. 2014-01 |
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A. Nicolás, H. Posadas, P. Peñil, E. Villar
"Automatic Concurrency generation through Communication Data Splitting based on UML-MARTE Models"
XXVIII Conference on Design of Circuits and Integrated Systems, San Sebastian, Noviembre, 2013
. 2013-11 |
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K. Grüttner, P.A. Hartmann, K. Hylla, S. Rosinger, W. Nebel, F. Herrera, E. Villar, C. Brandolese, W. Fornaciari, G. Palermo, C. Ykman-Couvreur, D. Quaglia, F. Ferrero (GMV), R. Valencia (GMV)
"The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration"
Microprocessors and Microsystems, V.37, N.8-C, Elsevier, pp.966-80. 2013-11 |
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R. Fernández, H. Posadas, E. Villar
"Early performance evaluation of Multi-OS embedded platforms using native simulation"
Euromicro Conference on Digital System Design, DSD 2013, IEEE, doi: 10.1109/DSD.2013.131. 2013-09 |
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H. Posadas, E. Villar, et al.
"EU FP7-288307 PHARAON project: Parallel and heterogeneous architecture for real-time applications"
Euromicro Conference on Digital System Design, DSD 2013, IEEE, doi: 10.1109/DSD.2013.47. 2013-09 |
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P. Peñil, P. Sánchez, D. de la Fuente, J. Barba, J.C. López
"UML/MARTE methodology for automatic SystemC code generation of OPENMAX multimedia applications
"
Euromicro Conference on Digital System Design, DSD 2013, IEEE. 2013-09 |
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P. Peñil, H. Posadas, A. Nicolás, E. Villar, D. Calvo (TED)
"Code Synthesis of UML/MARTE models for physical platforms considering resource-specific codes"
IV Jornadas de Computación Empotrada, Sarteco 2013. 2013-09 |
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H. Posadas, P. Peñil, A. Nicolás, E. Villar
"System synthesis from UML/MARTE models: The PHARAON approach"
Electronic System Level Synthesis Conference, ESLsyn, 2013, IEEE. 2013-05 |
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Á. Díaz, J. González, P. Sánchez, P. González
"Virtual platform for power and security analysis of wireless sensor network"
SPIE 2013. 2013-04 |
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Á. Díaz, P. Sánchez, J. Sancho, J. Rico
"Wireless Sensor Network Simulation for Security and Performance Analysis"
DATE 2013. 2013-03 |
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P. González, J. González, P. Sánchez
"OpenMP performance analysis for many-core platforms with non-uniform memory access"
IJCSI Volume 10, Issue 2. 2013-03 |
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F. Herrera, H. Posadas, P. Peñil, E. Villar, P. Sánchez, P. González, F. Ferrero (GMV), R. Valencia (GMV)
"A MDD Methodology for the Specification and Performance Estimation of Embedded Systems"
Tutorial B: Advanced Techniques for Power-Aware System-Level Prototyping, DATE'13. 2013-03 |
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E. Villar, H. Posadas
"SW simulation technologies in virtual platforms"
Class 6: "Embedded SW Development on Virtual Platforms - Ready for Industrial Deployment?", Embedded World 2013, Nuremberg. 2013-02 |
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H. Posadas, P. Peñil, A. Nicolás, E. Villar
"Automatic synthesis of Embedded SW Communications from UML/MARTE models supporting memory-space separation"
XXVII Conference on Design of Circuits and Integrated Systems, DCIS'12. 2012-11 |
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F. Herrera, I. Ugarte, E. Villar
"Towards automated implementation of adaptive systems from abstract SystemC specifications"
Design Automation of Embedded Systems, Springer. 2012-11 |
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R. Varona, E. Villar, A-I. Rodríguez (GMV), F. Ferrero (GMV), E. Alaña (GMV)
"Architectural Optimization & Design of Embedded Systems based on AADL Performance Analysis"
American Journal of Computer Architecture, V.1, N.2, Scientific & Academic Publishing. 2012-11 |
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Á. Díaz, P. Sánchez, J. Sancho, J. Rico
"Simulation of attacks in Wireless Sensor Network"
DCIS 2012. 2012-11 |
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P. González, P. Sánchez, J. González
"A virtual Platform for performance estimation of OpenMP Programs"
DCIS 2012. 2012-11 |
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P. González, J. González, P. Sánchez
"An approach for algorithm parallelization oriented to a many-core implementation"
ISPA 2012. 2012-11 |
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H. Posadas, P. Peñil, A. Nicolás, E. Villar
"UML/MARTE methodology for high-level system estimation and optimal synthesis"
MeCoES - Metamodeling and Code Generation for Embedded Systems, ESWeek 2012. 2012-10 |
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F. Herrera, H. Posadas, P. Peñil, E. Villar, F. Ferrero (GMV), R. Valencia (GMV)
"A MDD Methodology for Specification of Embedded Systems and Automatic Generation of Fast Configurable and Executable Performance Models"
ESWeek 2012 Compilation Proceedings, CoDes+ISSS’12, ACM. 2012-10 |
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F. Herrera, H. Posadas, P. Peñil, E. Villar, F. Ferrero (GMV), R. Valencia (GMV)
"The CompleX Eclipse Framework for UML/MATE Specification and design Space Exploration of Embedded Systems"
Proceedings of the 2012 Conference on Design & Architectures for Signal & Image Processing, DASIP 2012, IEEE. 2012-10 |
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H. Posadas, E. Villar
"Using Technical Documents as Support for Developing Competences in HW/SW Design"
IEEE International Symposium on Computers in Education, SIIE 2012. 2012-10 |
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P. Peñil, H. Posadas, A. Nicolás, E. Villar
"Automatic synthesis from UML/MARTE models using channel semantics"
International Workshop on Model-Based Arquitecting and Construction of Embedded Systems, ACES-MB 2012, doi: 10.1145/2432631.2432640. 2012-09 |
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Á. Díaz, P. Peñil, P. Sánchez, J. Sancho, J. Rico
"Modeling and Simulation of Secure Wireless Sensor networks"
Proceedings of the 2012 Forum on Specification and Design Languages, FDL'2012, IEEE. 2012-09 |
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Á. Díaz, R. Diego, P. Sánchez
"Virtual Platform for Wireless Sensor Network"
DSD Euromicro 2012. 2012-09 |
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F. Colas-Bigey, A. Terechko, H. Posadas, E. Villar, P. Peñil, F. Broekaert, C. Couvreur, M. Bourdelles, S. Li, L. Lavagno, A. Cohen
"Definition of tool interfaces and integrated design flow"
Deliverable D1.2 of the FP7 Pharaon Project. 2012-06 |
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H. Posadas, E. Villar, P. Peñil, F. Broekaert, C. Chantal, L. Lavagno, A. Terechko, M. Bourdelles, S. Li
"System specification methodology"
Deliverable D1.3 of the FP7 Pharaon Project. 2012-06 |
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P. Peñil, F. Herrera, E. Villar
"Formal Support for Untimed MARTE-SystemC Interoperability"
T. Kazmierski & A. Morawiec (Eds.): "Systems Specification and Design Languages", Lecture Notes in Electrical Engineering, V.106, Springer. 2012-06 |
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F. Herrera, P. Peñil, E. Villar, F. Ferrero (GMV), R. Valencia (GMV)
"The COMPLEX Eclipse framework for UML/MARTE Specification of Embedded Systems and automatic generation of executable models for Design-Space Exploration"
University Booth, DATE 12, Dresden. 2012-03 |
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P. Peñil, F. Herrera, E. Villar
"Formal Foundations for the Generation of Heterogeneous Executable Specifications in SystemC from UML/MARTE Models"
Kiyofumi Tanaka: "Embedded Systems - Theory and Design Methodology", InTech, Croatia. 2012-02 |
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E. Villar, H. Posadas
"SW simulation technologies in virtual platforms"
Class 6: "Embedded SW Development on Virtual Platforms - Ready for Prime Time?", Embedded World 2012, Nuremberg. 2012-02 |
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H. Posadas, Á. Díaz, E. Villar
"SW Annotation Techniques and RTOS Modeling for Native Simulation of Heterogeneous Embedded Systems"
Kiyofumi Tanaka: "Embedded Systems - Theory and Design Methodology", InTech, Croatia. 2012-02 |
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Elena Alaña, Francisco Ferrero, Ana Isabel Rodríguez, Raúl Valencia, Eric Conquet, Juan Antonio Puente, Juan Zamorano, F. Herrera, R. Varona
"Component-based technologies for HW/SW Co-Design"
Embedded Real Time Software and Systems-ERTS2. Toulouse. France. 2012-02 |
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P. González, P. Sánchez
"An approach for modelling parallelization in the P2012"
P2012 Developers Conference. Grenoble.. 2011-12 |
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P. González, P. Sánchez, J. González
"Hardware Performance Estimation by Dynamic Scheduling"
Proceedings FDL. 2011-12 |
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P. González, J. González, P. Sánchez
"Hardware Performance estimation by Dynamic Scheduling II"
Proceedings DCIS2011. 2011-12 |
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H. Posadas, E. Villar
"Automatic Communication Modeling for Early Exploration of HW/SW Allocation Based on Native Co-simulation"
XXVI Conference on Design of Circuits and Integrated Systems, DCIS'11. 2011-11 |
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D. Calvo, J. Pérez, P. González, R. Diego, Á. Díaz, P. Sánchez
"Design, modeling and development of an efficient comunication infrastructure for networking applications"
XXVI Conference on Design of Circuits and Integrated Systems, DCIS'11. 2011-11 |
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H. Posadas, E. Villar, Dominique Ragot, Marcos Martinez
"Early, time-approximate modeling of multi-OS linux platforms in a systemC co-simulation environment"
Int. Journal on Computer Systems Science & Engineering, Vol 26 No 6. 2011-11 |
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C. Silvano, W. Fornaciari, E. Villar
"Multi-objective Design Space Exploration of Multiprocessor SoC
Architectures: the MULTICUBE Approach"
Springer, New York, USA
. 2011-10 |
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H. Posadas, S. Real, E. Villar
"M3-SCoPE: Performance Modeling of Multi-Processor Embedded Systems for Fast Design Space Exploration"
C. Silvano, W. Fornaciari & E. Villar (Eds.): "Multi-objective Design Space Exploration of Multiprocessor SoC Architectures: the MULTICUBE Approach", Springer, New York, USA. 2011-10 |
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M. Martínez, D. Ferrúz, H. Posadas, E. Villar
"High-level modeling and exploration of a powerline communication network based on System-on-Chip"
C. Silvano, W. Fornaciari & E. Villar (Eds.): "Multi-objective Design Space Exploration of Multiprocessor SoC Architectures: the MULTICUBE Approach", Springer, New York, USA. 2011-10 |
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E. Villar, H. Posadas
"Native Power Estimation for Embedded System Design-Space Exploration"
PATMOS'11, Facultad de Informática, UCM, Madrid. 2011-09 |
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F. Herrera, E. Villar
"A Framework for the Generation from UML/MARTE Models of IP/XACT HW Platform Descriptions for Multi-Level Performance Estimation
"
Proceedings of the Forum of Design and Specification Languages 2011 (FDL'2011). 2011-09 |
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R. Varona, V. Fernández, E. Villar
"HWSW Co-Design Survey"
Deliverable R1-2 of the ESTEC HW/SW Co-Design Project. 2011-05 |
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P. Peñil, F. Herrera, E. Villar
"Towards SystemC Code Generation from UML/MARTE Concurrent System-Level Models "
W6: 2nd Workshop on Model Based Engineering for Embedded Systems Design, DATE 2011. 2011-03 |
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D. Calvo, P. Botella, H. Posadas, P. Sánchez, E. Villar
"Automatic Generation of HdS System Model for System Simulation using IP-XACT"
Workshop W7: Hardware Dependent Software Solutions for SoC Design, DATE 2011. 2011-03 |
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F. Herrera, E. Villar
"Generation of Abstract IP/XACT Platform Descriptions from UML/MARTE for System-Level Performance Estimation
"
W6: 2nd Workshop on Model Based Engineering for Embedded Systems Design, DATE 2011. 2011-03 |
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D. Calvo, P. González, H. Posadas, P. Sánchez, E. Villar, Andrea Acquaviva, Enrico Macii, Claudio Parrella, Mateo Giaconia
"SCoPE: SystemC Cosimulation and Performance Estimation. Application to Power and Thermal-Aware Design"
University Booth, DATE 11, Grenoble. 2011-03 |
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D. Calvo, P. González, L. Diaz, Alvaro Diaz, Pablo Sanchez, D. Gutiérrez (TTI), F. Alcalá (VS)
"Smart video processing in MPSoC demonstrator"
Deliverable DA2.3b of Artemis SCALOPES Project. 2011-03 |
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R. Varona, E. Villar, A-I. Rodríguez (GMV)
"Ravenscar Computational Model compliant AADL Simulation on LEON2"
International Symposium on Information System and Software Engineering, ISSE 2011
. 2011-03 |
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D. Calvo, P. González, L. Diaz, H. Posadas, P. Sánchez, E. Villar, Andrea Acquaviva, Enrico Macii
"A Multi-Processing Systems-on-Chip Native Simulation Framework for Power and Thermal-Aware Design"
ASP Journal on Low-Power Electronics (JOLPE): Special Issue on Low Power Design and Verification Techniques
. 2011-02 |
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H. Posadas, L. Diaz, E. Villar
"Fast Data-Cache Modeling for Native Co-Simulation
"
Asia and South Pacific Design Automation Conference, ASP-DAC 2011. 2011-01 |
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Wolfgang Mueller, Da He, Fabian Mischkalla, P. Peñil, E. Villar
"The SATURN Methodology for the Co-Verification of Embedded Systems(Final Version)"
Deliverable D3.5 the FP7-216807 SATURN Project. 2010-12 |
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E. Villar, P. Peñil, et. al.
"Final Project Activity report and Project Management Report"
Deliverable D1.3 of the FP7-216807 SATURN Project. 2010-12 |
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Nikolaos Mitas, Dimitrios Kritharidis, Florent Azcarate, Manuel Carballeda, Philippe Hébrard, P. Peñil
"Test Cases Design Implementation and Evaluation (second increment)"
Deliverable D5.4 the FP7-216807 SATURN Project. 2010-12 |
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Adrian Larkham, P. Peñil, E. Villar, et. al.
"Final Plan for Use and Dissemination of Foreground"
Deliverable D6.5 the FP7-216807 SATURN Project. 2010-12 |
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Adrian Larkham, P. Peñil, E. Villar, et. al.
"Final Project Report"
Deliverable D1.4 the FP7-216807 SATURN Project. 2010-12 |
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D. Calvo, H. Posadas, E. Villar, Francisco Alcalá, David Gutierrez
"Guidelines for System-level design, integration and optimization"
Deliverable DT4.3.6 of the Artemis Scalopes Project. 2010-12 |
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D. Calvo, P. Botella, L. Diaz, Saeid Azmoodeh, Francisco Barat, E. Villar, Philippe Millet
"Final report on CPD System component and model implementation"
Deliverable DT2.3.2 of the Artemis Scalopes project. 2010-11 |
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P. Botella, P. Sánchez, H. Posadas
"Automatic Generation of SystemC SMP Models for HW/SW Co-Simulation"
XXV Conference on Design of Circuits and Integrated Systems, DCIS'10. 2010-11 |
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P. González, P. Sánchez, L. Diaz
"Embedded software execution time estimation at different abstraction levels"
XXV Conference on Design of Circuits and Integrated Systems, DCIS'10. 2010-11 |
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H. Posadas, E. Villar
"Native Co-Simulation of TCP/IP-Based Embedded Systems in SystemC"
XXV Conference on Design of Circuits and Integrated Systems, DCIS'10. 2010-11 |
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J. Pérez, P. Sánchez
"Real-Time Voxel-Based Visual Hull Reconstruction"
XXV Conference on Design of Circuits and Integrated Systems, DCIS'10. 2010-11 |
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Gianluca Palermo, Carlo Brandolese, Francisco Ferrero, Gunnar Schomaker, Claus Brunzema, Kim Gruettner, Kai Hylla, Bart Vanthournout, Davide Quaglia, Luciano Lavago, Massimo Poncino, Emanuel Vaumorin, Chantal Couvreur, Saif Ali Butt, F. Herrera
"Definition of application, stimuli and platform specification, and definition of tool interfaces"
Documento Entregable D1.2.1 del proyecto COMPLEX,
http://complex.offis.de
. 2010-10 |
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D. Calvo, E. Villar, Phillipe Millet, Francisco Barat, Saeid Azmoodeh, et all
"CPD Design Flow & Modeling Framework (Final version)"
Deliverable DT2.4.2 of the Artemis Scalopes project. 2010-10 |
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H. Posadas, L. Diaz, E. Villar
"Método y sistema de modelado de memoria caché"
Oficina Española de Patentes y Marcas. OEPM. 2010-10 |
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P. Peñil, F. Herrera, E. Villar
"Formal Foundations for MARTE-SystemC Interoperability"
Forum on specification & Design Languages 2010, FDL'2010, IEEE. 2010-09 |
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V. Fernández, F. Herrera, E. Villar
"Formal Support for Untimed SystemC specifications: Application to high-level synthesis"
Forum on specification & Design Languages 2010, FDL'2010, IEEE. 2010-09 |
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P. Peñil, E. Villar, Wolfgang Mueller, Da He, Fabian Mischkalla
"Code Generation and Heterogeneous Run-Time Environments for the Co-Verification of Embedded Systems (second increment)"
Deliverable D3.4 the FP7-216807 SATURN Project. 2010-09 |
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W. Mueller, D. He, F. Mischkalla, A. Wegele, P. Whiston, P. Peñil, E. Villar, N. Mitas, D. Kritharidis, F. Azcarate, M. Carballeda
"The SATURN Approach to SysML-Based HW/SW Codesign"
IEEE Annual Symposium on VLSI, ISVLSI'10. 2010-07 |
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C. Silvano, W. Fornaciari, G. Palermo, V. Zaccaria, F. Castro, M. Martinez, S. Bocchio, R. Zafalon, P. Avasare, G. Vanmeerbeeck, C. Ykman-Couvreur, M. Wouters, C. Kavka, L. Onesti, A. Turco, U. Bondi, G. Mariani, H. Posadas, E. Villar, C. Wu, F. Dongrui, Z. Hao, T. Shibin
"Multi-Objective Design Space Exploration of Multi-Core Architectures"
IEEE Annual Symposium on VLSI, ISVLSI'10. 2010-07 |
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D. Calvo, E. Villar, Phillipe Millet, Saeid Azmoodeh, Francisco Barat, et all
"CPD Design Flow & Modelling Framework"
Deliverable DT2.4.1 of the Artemis Scalopes project. 2010-06 |
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Patricia Botella, P. González, Pablo Sánchez, Francisco Alcalá, Mario Virgliar, et all
"Embedded and low-power surveillance systems: Final specification release"
Deliverable DA2.2 of the Artemis Scalopes project. 2010-06 |
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E. Villar
"Formalization of the MARTE/SystemC interoperability for HW/SW co-design (Invited Speech)"
Artist MoBE-RTES Workshop, Carmona (Sevilla). 2010-05 |
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H. Posadas, E. Villar, Dominique Ragot, M. Martínez (DS2)
"Early Modeling of Linux-based RTOS Platforms in a SystemC Time-Approximate Co-Simulation Environment"
IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC'10). 2010-05 |
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F. Broekaert, N. Ventroux, D. Calvo, Á. Díaz, E. Villar, F. Alcalá, D. Gutiérrez
"System-level performance simulation: User Manuals & Prototype tools"
Deliverable DT4.3.1a of the Artemis Scalopes project. 2010-05 |
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J. Castillo, H. Posadas, E. Villar, M. Martínez (DS2)
"Fast Instruction Cache Modeling for Approximate Timed HW/SW Co-Simulation "
20th Great Lakes Symposium on VLSI (GLSVLSI'10), Providence, USA. 2010-05 |
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M. Carballeda, N. Mitas, D. Kritharidis, F. Azcárate, P. Hebrard, E. Villar, P. Peñil
"Test Cases Specification (second increment)"
Deliverable D5.3 the FP7-216807 SATURN Project. 2010-04 |
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J. Pérez, V. Fernández, P. Sánchez
"Optimizing Data-Flow Graphs with Min/Max, Adding and Relational Operations"
Design Automation and Test in Europe 2010, DATE'10. 2010-03 |
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R. Varona, E. Villar
"AADS+: AADL simulation including the Behavioral Annex"
Proceedings of the 15th IEEE International Conference on Engineering of Complex Computer Systems. 2010-03 |
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D. Calvo, E. Villar, A. Aquaviva, F. Bruschi
"Final Report on Architecture Modeling"
Deliverable DT4.2.2 of the Artemis Scalopes project. 2010-03 |
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P. Peñil, H. Posadas, E. Villar
"Formal Modeling for UML/MARTE Concurrency Resources"
Proceedings of the 15th IEEE International Conference on Engineering of Complex Computer Systems. 2010-03 |
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H. Posadas, E. Villar
"Modeling Separate Memory Spaces in Native Co-simulation with SystemC for Design Space Exploration
"
2PARMA Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures
. 2010-02 |
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E. Villar, D. Calvo, A. Aquaviva, F. Bruschi
"Preliminary Report on architecture modeling and tool prototyping"
Deliverable DT4.2.1 of the Artemis Scalopes project. 2010-02 |
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P. Peñil, J. Medina (CTR), H. Posadas, E. Villar
"Generating Heterogeneous Executable Specifications in SystemC from UML/MARTE Models"
in "Innovations in Systems and Software Engineering", V.6, N.1-2, March, Springer. 2009-12 |
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E. Villar, P. Peñil, et. al.
"Updated Plan for Use and Dissemination of Foreground"
Deliverable D6.4 the FP7-216807 SATURN Project. 2009-12 |
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E. Villar, P. Peñil, et. al.
"Second Project Activity Report and Project Management Report "
Deliverable D1.2 the FP7-216807 SATURN Project. 2009-12 |
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H. Posadas, G. de Miguel, E. Villar
"Automatic generation of modifiable platform models in SystemC for Automatic System Architecture Exploration "
XXIV Conference on Design of Circuits and Integrated Systems, DCIS 2009, Zaragoza, Spain. 2009-11 |
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F. Pétrot (TIMA), E. Villar
"High Speed Multi-Processors System-On-Chip Simulation Platforms for Hardware Dependent Software Development"
1st SoftSoC Workshop, Grenoble. 2009-10 |
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C. Fabre (CEA), E. Villar, E. Vaumorin (MDS)
"Hardware-defined Software: Concepts & Architecture"
1st SoftSoC Workshop, Grenoble. 2009-10 |
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F. Herrera, E. Villar
"Local Application of Simulation Directed for Exhaustive Coverage of Schedulings in SystemC Specifications"
Proceedings of the Forum on specification and Design Languages, FDL'09, IEEE, 2009. 2009-09 |
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H. Posadas, E. Villar
"Automatic HW/SW interface modeling for scratch-pad & memory mapped HW components in native source-code co-simulation (Best Paper Award)"
A. Rettberg, M. Zanella, M. Amann, M. Keckeiser & F. Rammig (Eds.): "Analysis, Architectures and Modelling of Embedded Systems", Springer, 2009. 2009-09 |
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H. Posadas, J. Castillo, D. Quijano, V. Fernández, E. Villar, Marcos Martínez (DS2)
"SystemC Platform Modeling for Behavioral Simulation and Performance Estimation of Embedded Systems"
L. Gomes and J. M. Fernandes (Eds.): “Behavioral Modeling for Embedded Systems and Technologies: Applications for Design and Implementation”, IGI Global. 2009-07 |
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R. Varona, E. Villar
"AADS User's Manual"
Deliverable 3.4.1 of the SPICES project. 2009-07 |
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R. Varona, E. Villar
"AADL simulation and performance analysis in SystemC"
14th IEEE International Conference on Engineering of Complex Computer Systems, Postdam. 2009-06 |
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P. Peñil, E. Villar, H. Posadas, Julio Medina (CTR)
"Executable SystemC specification of the MARTE generic concurrent and communication resources under different Models of Computation"
Workshop on the Definition, evaluation, and exploitation of modelling and computing standards for Real-Time Embedded Systems, STANDRTS'09
Satellite Workshop of the the 21st EuroMicro Conference on Real-Time Systems, Dublin. 2009-06 |
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E. Villar
"SATURN presentation"
Workshop on the Definition, evaluation, and exploitation of modelling and computing Standards for Real-Time Embedded Systems, STANDRTS'09. Satellite Workshop of the the 21st EuroMicro Conference on Real-Time Systems, Dublín. 2009-06 |
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R. Varona, E. Villar
"User Manual of AADS v.2.0"
Deliverable D3.4.1: "SystemC Generator-final release" of the SPICES project. 2009-05 |
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R. Varona, E. Villar
"AADS: AADL simulation and performance analysis in SystemC"
Software demonstration at the DATE’09 University Booth, Nice, April, 2009. 2009-04 |
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E. Villar, P. Peñil, et. al.
"Draft Roadmap Definition"
Deliverable D6.3 the FP7-216807 SATURN Project. 2009-04 |
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F. Herrera
"Especificación Heterogénea y Generación Automática de Software para Sistemas Embebidos desde SystemC"
Universidad de Cantabria. 2009-02 |
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P. Peñil, E. Villar, et. al.
"Specification of a MDA-based framework with embedded systems verification support"
Deliverable D4.2 of the FP7-216807 SATURN Project. 2009-02 |
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S. Real, F. Herrera, E. Villar
"Modelling of SW. Final library elements."
Deliverable D1.2b of the ANDRES project. 2009-01 |
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F. Herrera, E. Villar, P. A. Hartmann
"Specification of HW/SW adaptive Embedded Systems in
SystemC"
Proceedings of the Forum on specification and Design Languages, FDL'08, IEEE, 2008. 2008-09 |
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V. Fernández, E. Villar
"SystemC"
ARTIST Survey of Programming Languages.
Alan Burns (Editor). 2008-08 |
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M. Díez, E. Villar, M. Martínez (DS2)
"HdS code generation tool development"
Deliverable DS2-T4.5-Q2-08 of the Medea+ 2A708 LoMoSa+ Project. 2008-08 |
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E. Villar, P. Peñil, et. al.
"Plan for Use and Dissemination of Foreground"
Deliverable D6.2 the FP7-216807 SATURN Project. 2008-08 |
|
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R. Varona, E. Villar
"User Manual of AADS"
Deliverable D3.4.1: "SystemC Generator-first release" of the SPICES project. 2008-07 |
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J. Barreda, P. Sánchez, Jorge Ocón
"Integration of Domain-Specific Models into a MDA Framework for
Time-Critical Embedded Systems"
Sixth Workshop on Intelligent Solutions in Embedded Systems WISES 08. 2008-07 |
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F. Herrera, E. Villar, C.Grimm, M.Damm, J.Haase
"Heterogeneous Specification with HetSC and SystemC-AMS. Widening the support of MoCs in SystemC
"
E. Villar (Ed.): "Embedded Systems Specification and Design Languages", The CHDL Series V.10, Springer, pp-107-121. 2008-06 |
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J. Haase, P. A. Hartmann, F. Herrera
"Initial Version of Integrated Framework."
Deliverable D1.6a of the ANDRES project. 2008-06 |
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K.Gruettner, A. Herrholz, P. A. Hartmann, F. Herrera, E. Villar
"Interface Synthesis Concept"
Deliverable D2.3a of the ANDRES project. 2008-06 |
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E. Villar
"Embedded Systems Specification and Design Languages: Selected contributions from FDL'07"
The CHDL Series V.10, Springer. 2008-06 |
|
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J. Haase, M. Damm, C. Grimm, F. Herrera, E. Villar
"Bridging MoCs in SystemC Specifications of Heterogeneous Systems"
EURASIP Journal on Embedded Systems, Special Issue "C-Based Design of Heterogeneous Embedded Systems", Volume 2008 (2008), Article ID 738136, 16 pages. 2008-05 |
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C. Grimm, A. Jantsch, S. Shukla, E. Villar
"Editorial: C-Based Design of Heterogeneous Embedded Systems"
EURASIP Journal on Embedded Systems, Special Issue "C-Based Design of Heterogeneous Embedded Systems", Volume 2008 (2008). 2008-05 |
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R. Varona, E. Villar
"AADS (AADL SystemC Simulator)"
Deliverable D3.4.1: "SystemC Generator-first release", del proyecto SPICES. 2008-04 |
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J. Castillo, H. Posadas, E. Villar, Marcos Martínez (DS2)
"Energy Consumption Estimation Technique in Embedded Processors with Stable Power Consumption based on Source-Code Operator Energy Figures"
XXII Conference on Design of Circuits and Integrated Systems, DCIS'07 . 2007-11 |
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J. Haase, M. Damm, C. Grimm, F. Herrera, E. Villar
"Using Converter Channels within a Top-Down Design Flow in SystemC"
The 15th Austrian Workhop on Microelectronics, Graz, Austria. 2007-10 |
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F. Herrera, E. Villar, C. Grimm, M. Damm, J. Haase
"A general approach to the interoperability of HetSC and SystemC-AMS"
Proceedings of the Forum on Design Languages 2007, FDL'07. Barcelona. 2007-09 |
|
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H. Posadas, D. Quijano, E. Villar, Marcos Martínez (DS2)
"Protocol Bus Modeling using inheritance with TLM2.0"
Proceedings of the Forum on Design Languages, FDL'07. Barcelona. 2007-09 |
|
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E. Villar, E. de las Heras
"SystemC-AADL interoperability"
ECSI Industrial Workshop: “System Design in Avionics and Space Industry”, Barcelona. 2007-09 |
|
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F. Herrera, E. Villar
"A Framework for Heterogeneous Specification and Design of Electronic Embedded Systems in SystemC"
ACM Transactions on Design Automation of Electronic Systems, Special Issue on Demonstrable Software Systems and Hardware Platforms, V.12, Issue 3, N.22. 2007-08 |
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A.Herrholz, F. Oppenheimer, P.A.Hartmann, A.Schallenberg, W. Nebel, C.Grimm, M.Damm, J.Haase, F.Brame, F. Herrera, E. Villar, I.Sander, A.Jantsch, A.-M.Foulliart, M.Martínez
"The ANDRES project: Analysis and Design of Run-time REconfigurable, heterogeneous Systems"
17th International Conference on Field Programmable Logic and Applications. Amsterdam. 2007-08 |
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J. Castillo, H. Posadas, D. Quijano, P. Sánchez, E. Villar
"HdS modeling library"
DS2-T3.4-Q2/07 Deliverable of the Medea+ 2A708 LoMoSa+ Project. 2007-06 |
|
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E. de las Heras, E. Villar
"Specification for SystemC-AADL interoperability"
IEEE Proceedings of the 5th International Workshop on Intelligent Solutions in Embedded Systems (WISES’07). 2007-06 |
|
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F. Herrera, E. Villar
"Modeling of Software. Initial Library elements"
Deliverable D1.2a of the IST 5-033511 ANDRES Project. 2007-06 |
|
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E. Villar, H. Posadas, Marcos Martínez (DS2)
"Efficient HdS simulation for MpSoC with NoC"
MEDEA+ Design Automation Conference, Grenoble. 2007-05 |
|
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|
A. Herrholz, F. Oppenheimer, A. Schallenberg, W. Nebel, C. Grimm, M. Damm, F. Herrera, E. Villar, A-M. Fouilliart, M. Martínez
"ANDRES- ANalysis and Design of run-time REconfigurable, heterogeneous Systems"
Workshop on "Adaptive Heterogeneous Systems-On-Chip and European Dimensions" in the Design Automation and Test in Europe 2007, DATE'07. 2007-04 |
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H. Posadas, D. Quijano, E. Villar, M. Martínez (DS2)
"SCoPE: SoC co-simulation and performance estimation in SystemC"
Software demonstration at the DATE’07 University Booth, Nice, April, 2007. 2007-04 |
|
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E. de las Heras, E. Villar
"UC Contribution to D2.1: Definition of Semantic for AADL"
Deriverable D2.1 of the SPICES project. 2007-02 |
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H. Posadas, J. Adámez, E. Villar, F. Escuder (DS2), F. Blasco (DS2)
"RTOS modeling in SystemC for Real-Time embedded SW simulation: A POSIX model"
Design Automation for Embedded Systems, V.10, N.4, Springer, pp.209-227. 2006-12 |
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H. Posadas, D. Quijano, E. Villar, F. Escuder (DS2), M. Martínez (DS2)
"TLM interrupt modelling for HW/SW co-simulation in SystemC"
XXI Conference on Design of Circuits and Integrated Systems, DCIS'06 . 2006-11 |
|
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E. Villar, F. Herrera
"SystemC as an Heterogeneous System Specification Language"
ARTIST2 Workshop on Models of Computation and Communication (MoCC'06), ETH, Zurich. 2006-11 |
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F. Herrera, E. Villar, Cristoph Grimm (TUV), Ingo Sanders (KTH), Axel Jantsch (KTH)
"Methodology for Specification of Adaptivity"
Deliverable D1.1a of the IST 5-033511 ANDRES Project. 2006-11 |
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F. Herrera, E. Villar
"Extension of the SystemC kernel for Simulation Coverage Improvement of
System-Level Concurrent Specifications"
Proceedings of the Forum on Design Languages (FDL’06), Darmstadt, ECSI. 2006-09 |
|
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F. Herrera, E. Villar
"A Framework for Embedded System Specification under Different Models of Computation in SystemC"
Proc. of DAC'06, ACM. 2006-07 |
|
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F. Herrera, E. Villar
"Mixing Synchronous Reactive and Untimed MoCs in SystemC"
"Applications of Specification and Design Languages for SoCs", A. Vachoux (Ed.), CHDL Series, Springer. 2006-07 |
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D. Quijano, H. Posadas, P. Sánchez, E. Villar, Marcos Martínez (DS2)
"Specification of HdS modeling methodology"
DS2-T3.4-Q2/06 Deliverable of the Medea+ 2A708 LoMoSa+ Project. 2006-06 |
|
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H. Posadas, J. Adámez, E. Villar, Emilio Arias (DS2)
"SystemC Execution Support Implementation"
D3.8.1 Deliverable of the ITEA IP 03002 Merced Project. 2006-06 |
|
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|
H. Posadas, J. Adámez, P. Sánchez, E. Villar, Francisco Blasco (DS2)
"POSIX modeling in SystemC"
proc. of the 11th Asia and South Pacific Design Automation Conference, ASP-DAC'06, IEEE. 2006-01 |
|
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H. Posadas, J. Adámez, E. Villar
"SystemC Execution Support Implementation: First Draft"
Documento Entregable UC_T3.8_Q2/06. 2005-12 |
|
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|
H. Posadas, E. Villar, Francisco Blasco
"Real-time Operating System modeling in SystemC for HW/SW co-simulation"
XX Conference on Design of Circuits and Integrated Systems, DCIS'05, IST Lisboa.. 2005-11 |
|
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|
|
I. Ugarte, P. Sánchez
"Formal Meaning of Coverage Metrics in Simulation-based Hardware Design Verification"
IEEE International High-Level Design Validation and Test Workshop
California. 2005-11 |
|
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|
|
F. Herrera, P. Sánchez, E. Villar
"Heterogeneous system-level specification in SystemC"
"Advances in Design and Specification Languages for SoC", P. Boulet (Ed.), CHDL Series, Springer. 2005-10 |
|
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E. Villar
"Introduction"
"Advances in Design and Specification Languages for SoC", P. Boulet (Ed.), CHDL Series, Springer. 2005-10 |
|
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F. Herrera, E. Villar
"Mixing synchronous reactive and untimed models of computation in SystemC"
Proceedings of the Forum on Design Languages (FDL’05), Lausanne, ECSI. 2005-09 |
|
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|
H. Posadas, J. Adámez, E. Villar
"Requirements for a ‘trying’ environment in System context"
D2.5.1 Deliverable of the ITEA IP 03002 Merced Project. 2005-06 |
|
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|
H. Posadas, J. Adámez, E. Villar
"Requirements and definition of a common simulation environment: University of Cantabria contribution (First draft)"
Preliminar_DS2_D2.5.2. 2004-12 |
|
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H. Posadas, F. Herrera, V. Fernández, P. Sánchez, E. Villar, F. Blasco
"Single Source Design Environment for Embedded Systems Based on SystemC"
Design Automation for Embedded Systems, V.9, N.4, Springer, pp.293-312. 2004-12 |
|
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F. Herrera, P. Sánchez, E. Villar
"Heterogeneous system-level specification in SystemC"
Proceedings of the Forum on Design Languages (FDL’04), Lille, ECSI. 2004-09 |
|
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|
F. Herrera, P. Sánchez, E. Villar
"Modeling and design of CSP, KPN and SR systems in SystemC"
"Languages for System Specification", C. Grimm (Ed.), CHDL Series, Kluwer Academic Publisher. 2004-06 |
|
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I. Ugarte, P. Sánchez
"Path-oriented Assertion Checking of Cyclic Behavioral Descriptions"
Formal Methods and Models for Co-Design MEMOCODE'04
California. 2004-06 |
|
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|
M. Bolado, H. Posadas, Javier Castillo, Pablo Huerta, P. Sánchez, Carlos Sánchez, Häkan Fouren, Francisco Blasco
"Platform based on open-source cores for industrial applications"
Proc. of DATE'04, IEEE CS Press. 2004-02 |
|
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H. Posadas, F. Herrera, P. Sánchez, E. Villar, F. Blasco
"System-Level Performance Analysis in SystemC"
proc. of DATE'04, IEEE CS Press. 2004-02 |
|
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|
M. Bolado, J. Castillo, P. Huerta, H. Posadas, P. Sánchez
"Implementation of a microprocessor core"
DS2-WP5-Q4/03 Deliverable of the Medea+ A511 TOOLIP Project. 2003-12 |
|
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E. Villar, P. Sánchez, F. Blasco, M. Radetzki, A. Vörg, Y. Wenhao
"Reusability of Microprocessor cores"
proc. of the MEDEA+ Design Automation Conference, Stuttgart. 2003-11 |
|
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I. Ugarte, P. Sánchez
"Functional Vector Generation for Assertion-Based Verification at Behavioral Level Using Interval Analysis"
IEEE International High Level Design Validation and Test Workshop HLDVT’03, San Francisco, CA. 2003-11 |
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M. Bolado, J. Castillo, P. Huerta, H. Posadas, P. Sánchez
"Executable specification of a microprocessor core"
UC-T2.1-Q3/03 Deliverable of the Medea+ A511 TOOLIP Project. 2003-09 |
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F. Herrera, P. Sánchez, E. Villar
"Modeling and design of CSP, KPN and SR systems in SystemC"
Proceedings of the Forum on Design Languages FDL'03, Frankfurt, ECSI. 2003-09 |
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I. Ugarte, P. Sánchez
"System Verification Based on Modified Interval Analysis"
European test Workshop, ETW’03. 2003-05 |
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F. Herrera, H. Posadas, P. Sánchez, E. Villar
"Systematic Embedded Software Generation from SystemC"
proc. of DATE'03, IEEE CS Press. 2003-02 |
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F. Herrera, V. Fernández, P. Sánchez, E. Villar
"Embedded Software Generation from SystemC for Platform Based Design"
"SystemC Methodologies and Applications", Kluwer Academic Publishers. 2003-01 |
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F. Herrera, H. Posadas, P. Sánchez, E. Villar
"Systematic Embedded software generation from SystemC"
"Embedded Software for SoC", Kluwer Academic Publishers. 2003-01 |
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M. Bolado, J. Castillo, C. Sánchez, H. Posadas, P. Sánchez
"Functional specification of a microprocessor core"
UC-T2.1-Q4/02 Deliverable of the Medea+ A511 TOOLIP Project. 2002-12 |
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H. Posadas, F. Herrera, P. Sánchez, E. Villar
"Library for microprocessor core analysis"
UC-T1.3-Q4/02 Deliverable of the Medea+ A511 TOOLIP Project. 2002-12 |
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Francisco Blasco, E. Villar, F. Herrera
"System-Level Dynamic Estimation of Time Performance for Codesign based on SystemC and HW/SW platform"
XVII Conference on Design of Circuits and Integrated Systems DCIS'02, Santander. 2002-11 |
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E. Villar, Susana López, M. Bolado
"Design of first and second layers of a residential gateway ITD interface"
XVII Conference on Design of Circuits and Integrated Systems DCIS'02, Santander. 2002-11 |
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F. Herrera, H. Posadas, E. Villar
"Documento de requisitos técnicos de la biblioteca de perfilado"
UC/ToolIP/IR/03 Internal Report of the Medea+ A511 TOOLIP Project. 2002-11 |
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F. Herrera, P. Sánchez, E. Villar
"HW/SW interface implementation from SystemC for platform-based design"
Forum on Design Languages FDL'02, ECSI. 2002-10 |
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E. Villar, P. Sánchez, H. Posadas
"System-level reusability of microprocessor cores in a SystemC specification environment"
MEDEA+ Design Automation Conference. 2002-09 |
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F. Herrera, P. Sánchez, E. Villar
"Comparative study for the selection of the processor core for SystemC specification"
UC/ToolIP/IR/01 Internal Report of the Medea+ A511 TOOLIP Project. 2002-06 |
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F. Herrera, P. Sánchez, E. Villar
"First draft of the library for microprocessor core analysis"
UC/ToolIP/IR/02 Internal Report of the Medea+ A511 TOOLIP Project. 2002-06 |
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E. Villar
"A framework for specification and verification of timing constraints"
A. Mignotte, E. Villar & L. Horobin (Eds.): "System on Chip Design Languages: Best of FDL’01 & HDLCon’01", Kluwer Academic Publisher, pp.267-74. 2002-03 |
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I. Ugarte, P. Sánchez, E. Villar
"Metodología de Verificación y diseño para testabilidad digital"
Documento Entregable R3 del proyecto FEDER 1FD97-0791. 2002-03 |
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V. Fernández, F. Herrera, P. Sánchez, E. Villar
"Conclusiones: Metodología industrial de diseño de sistemas embebidos HW/SW"
Documento Entregable DF del proyecto FEDER 1FD97-0791. 2002-02 |
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V. Fernández, E. Villar, F. Herrera
"System-Level Specification in SystemC of a Residential Gateway"
16th Design of Circuits and Integrated Systems Conference, DCIS 2001. Oporto (Portugal). 2001-11 |
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F. Herrera, C. Camargo, E. Villar
"Embedded system design methodology based on SystemC"
Proc. of the Forum on Design Languages FDL01, Lyon, ECSI. 2001-09 |
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E. Villar
"Design of HW/SW Embedded Systems"
Servicio de Publicaciones de la Universidad de Cantabria. 2001-07 |
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E. Villar
"HW/SW embedded system specification"
"Design of HW/SW Embedded Systems". (Ed. E. Villar). Servicio de Publicaciones de la Universidad de Cantabria. 2001-07 |
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F. Herrera, V. Fernández
"Introduction to SystemC"
"Design of HW/SW Embedded Systems". (Ed. E. Villar), Servicio de Publicaciones de la Universidad de Cantabria. 2001-07 |
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P. Sánchez
"Embedded Software and RTOS"
"Design of HW/SW Embedded Systems", Edited by E. Villar, Servicio de Publicaciones de la Universidad de Cantabria. 2001-07 |
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V. Fernández, F. Herrera, E. Villar
"Especificación ejecutable del demostrador industrial"
Documento Entregable R2-C2 del proyecto FEDER 1FD97-0791. 2001-04 |
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F. Herrera, V. Fernández, R. Rodríguez, P. Sánchez, E. Villar
"Especificación del demostrador industrial"
Documento Entregable R2-C1 del proyecto FEDER 1FD97-0791. 2000-10 |
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F. Herrera, R. Rodríguez, V. Fernández, E. Villar
"Desarrollo de Metodologías Industriales de Diseño de Sistemas Embebidos HW/SW"
I Seminario del Programa Nacional de Tecnologías de la Información y las Comunicaciones (TEDEA 2000). Almagro (Ciudad Real). 2000-09 |
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S. Dey, D. Panigrahi, L. Chen, C. N. Taylor, K. Sekar, P. Sánchez
"Using a Soft Core in a SOC Design: Experiences with picoJava"
IEEE Design & Test of Computers. Pág. 60-71. 2000-07 |
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G. Gorla, E. Moser, W. Nebel, E. Villar
"System Specification Experiments on a Common Benchmark"
IEEE Design & Test of Computers, Pág. 22-32. 2000-07 |
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R. Rodríguez, E. Villar
"Metodología de co-diseño"
Documento Entregable R1 del proyecto FEDER 1FD97-0791. 2000-06 |
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R. Rodríguez, E. Villar
"Contribución al Deliverable D.3.1.B: "Evaluation of co-simualtion of the space application""
Deliverable D.3.1.B of the ESPRIT 26971 CoMES project. 1999-12 |
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P. Sánchez, S. Dey
"Simulation-based system-level verification using polynomials"
IEEE International High Level Design Validation and Test Workshop HLDVT’99, San Diego, CA. 1999-11 |
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F. Herrera, C. Sánz, I. Ugarte, E. Villar
"Specification Components: Reusability at the HW/SW system specification level"
proc. of the VHDL International Users Forum, IEEE CS. 1999-10 |
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R. Rodríguez, E. Villar
"Contribución al Deliverable D.2.2.B: "Architecture design and performance evaluation""
Deliverable D.2.2.B of the ESPRIT 26971 CoMES project. 1999-10 |
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R. Rodríguez, E. Villar
"Contribución al Deliverable D.3.1.A: "Specification of the case study detailed design""
Deliverable D.3.1.A of the ESPRIT 26971 CoMES project. 1999-09 |
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B. Foucault, J.P. Calvez, X. Lobao, S. Olcóz, E. Villar
"CoMES: CoDesign Methodology for Embedded Systems"
proc. European Multimedia, Microprocessor Systems and Electronic Commerce Conference, EMMSEC'99, Stockholm, Sweden. 1999-06 |
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E. Villar
"Contribución al Deliverable D.2.2.A: "Functional design of the case study""
Deliverable D.2.2.A of the ESPRIT 26971 CoMES project. 1999-04 |
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E. Villar, A. López
"Especificación de sistemas embebidos"
Sistemas digitales: Elementos para un diseño de alto nivel. Ed. Ediciones Uniandes. 1999-02 |
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E. Villar, D.B. de Vries and S. M. H. de Groot
"Functional design and Ada specification of the ATM sender for HW/SW co-design"
8th HCM BELSIGN Workshop. 1999-01 |
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A. López, M. Veiga, E. Villar
"Hardware/Software embedded system specification and design using Ada and VHDL"
Reliable Software Technologies-Ada-Europe'1999, Springer-Verlag.. 1999-01 |
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J.P. Deschamps, E. Villar
"Ada to VHDL translation in HW/SW co-design"
8th HCM BELSIGN Workshop. 1998-10 |
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V. Fernández
"Síntesis de Alto Nivel de Sistemas Digitales Altamente Testables"
Tesis Doctoral. Universidad de Cantabria.. 1998-09 |
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V. Fernández, P. Sánchez
"A Novel Approach To High-Level Test Synthesis Based On Controller Redefinition"
Proceedings of the European Test Workshop. Sitges, Spain. 1998-05 |
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V. Fernández, P. Sánchez
"Advanced Techniques for EMBEDDED SYSTEMS DESIGN & TEST, Capítulo 9, TEST SYNTHESIS OF DIGITAL SYSTEMS. "
Kluwer Academic Publishers. 1998-01 |
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E.Villar, M. Veiga
"Embedded system specification"
Advanced Techniques for Embedded Systems Design & Test, págs. 1-30. Kluwer Academic Publishers. 1998-01 |
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E. Villar, M. Veiga & M. G. Harbour
"Embedded system specification and design using Ada and VHDL"
First International Forum on Design Languages (FDL98). 1998-01 |
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A. López, M. Veiga, P. Sánchez, E. Villar
"ADA embedded system specification"
XII Design of Circuits and Integrated Systems Conference DCIS'97, Sevilla. 1997-11 |
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V. Fernández, P. Sánchez
"High-Level Test Synthesis based on controller redefinition"
IEE Electronics Letters, Vol. 33, No. 19, pp. 1596-1597. 1997-09 |
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V. Fernández, P. Sánchez
"Test Points Insertion For High-Level Test Synthesis"
Proceedings of the 4th Belsign Workshop. Santander, Spain. 1996-10 |
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H.W.A. Teunissen, D. B. de Vries, S.M. Heemstra de Groot, A. Antón, E. Villar
"HW/SW Co-Design of the ATM AAL3-5 Protocols"
4th HCM BELSIGN Workshop, Santander. 1996-10 |
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V. Fernández, P. Sánchez
"Partial Scan High-Level Synthesis"
European Design & Test Conference. Paris, France. 1996-03 |
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E. Villar
"VHDL in Spain"
VHDL International User´s Forum. Santa Clara, CA, USA. 1996-03 |
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P. Tabuenca, E. Villar, H. Veit, H.T. Vierhaus
"HS/SW co-design environment based on the CASTLE and FIRES tools: Use of C and VHDL as specification language"
SYDIS Publications 1993-1995, GMD. 1996-02 |
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Pedro Tabuenca Dopico
"Desarrollo de un Sistema Inteligente para Síntesis de Comportamiento: Aplicación al Co-diseño HW/SW"
Tesis Doctoral. Universidad de Cantabria. 1995-12 |
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E. Villar
"Level-0 VHDL synthesis syntax and semantics"
CENELEC TC117 ENV. 1995-12 |
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P. Tabuenca, E. Villar
"Entorno de co-diseño HW/SW basado en las herramientas CASTLE y FIRES: Uso de C y VHDL como lenguajes de especificación"
X Congreso de Diseño de Circuitos Integrados y Sistemas (DCIS95). Zaragoza. 1995-11 |
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E. Villar
"Part of Standardization activities: The synthesis package", Part 1, Vol.I"
Deliverable 204 of the ESPRIT 8370 ESIP project. 1995-10 |
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P. Tabuenca, E. Villar
"HW/SW co-design based on the CASTLE and FIRES tools: Methodology and application"
proc. of the 2nd HCM BELSIGN Workshop, Duisburg, Germany. 1995-09 |
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L. Entrena, S. Olcoz, P. Sánchez, E.Villar, J. Uceda, T. Riesgo
"Final report on the achievements of the ESIP fault modeling and simulation activity"
Deliverable 216 of the ESPRIT 8370 ESIP project. 1995-09 |
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V. Fernández, P. Sánchez, E. Villar
"A Novel High-Level Allocation Technique for Test"
Fourth Annual Atlantic Test Workshop. Corsica, France. 1995-07 |
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E. Villar, P. Sánchez
"CAD tools for synthesis"
proc. of the IEEE International Synposium on Industrial Electronics, ISIE'95, Athens, Greece. 1995-07 |
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V. Fernández, P. Sánchez, E. Villar
"Partial Scan High-Level Synthesis Strategy"
Second International Test Synthesis Workshop. Santa Barbara, CA (USA). 1995-05 |
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L. Entrena, L. Berrojo, S. Olcoz, P. Sánchez, E. Villar, J. Uceda, T. Riesgo
"Report on logic and RTL fault modeling"
Deliverable 214 of the ESPRIT 8370 ESIP project. 1995-03 |
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P. Tabuenca, E. Villar
"Integrating a design space exploration system for high-level synthesis into a HW/SW co-design environment"
1st HCM BELSIGN Workshop, Toledo, Spain. 1995-02 |
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E. Villar, M. Altmäe
"Language requirements for high-level synthesis"
CENELEC TC117 report. 1995-01 |
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E. Villar, A. Debreil
"Synthesis and formal proof language support"
CENELEC TC117 report. 1994-09 |
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E. Villar, L. Berrojo, A. Debreil, B. Fjellborj, M. Mentes, C-W. Lee, N. Jansson
"Standardization activities: The synthesis package"
Deliverable 203 of the ESPRIT 8370 ESIP project. 1994-07 |
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V. Fernández, P. Sánchez, Marta García, E. Villar
"Fault Modeling and Injection in VITAL Descriptions"
Proceedings of the Third Annual Atlantic Test Workshop, Nimes, France. 1994-06 |
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V. Fernández, P. Sánchez, E. Villar
"High Level Synthesis Guided by Testability Measures"
First International Test Synthesis Workshop, Santa Barbara, CA (USA). 1994-05 |
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E. Villar, P. Sánchez, V. Fernández
"High Level Synthesis with Testability Criteria"
2nd IEEE Annual Atlantic Test Workshop, Hanover, USA. 1993-06 |
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| Formación de ingenieros en técnicas de diseño y test de circuitos VLSI |
|
Y. Lechuga, R. Casanueva, M. Martínez
"Analisys of teaching methodologies for electronics in non-specialized engineering Studies"
Proceedings of the XXX Conference on Design of Systems and Integrated Circuits. DCIS 2015. 2015-11 |
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M.Martínez, S.Bracho, R.Mozuelos, M.A.Allende
"Tecnologías Colaborativas en un Curso de Circuitos Microelectrónicos"
Informática 2009, Segundo Simposio Internacional de Computación y Electrónica, La Habana (Cuba). 2009-02 |
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M. Martínez, M. Allende, R. Mozuelos, S. Bracho
"Microelectronics Distance Program with Extended Practical Work"
European Workshop on Microelectronics Education(EWME'2008). Budapest (Hungria). 2008-05 |
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M. Allende, R. Mozuelos, M. Martínez, S. Bracho
"Microelectronic Interactive Distance Course with On-line Measurement Laboratory"
3rd WSEAS International Conference on Engineering Education. Vouliaghmeni(Gr). 2006-07 |
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M. Allende, R. Mozuelos, M. Martínez, S. Bracho
"Microelectronics Interactive Distance Course with Advanced Experiments on MOS Transistors in an On-line Measurement Laboratory"
WSEAS Transaction on Advances in Engineering Education, issue 5, Vol 3, 263-268. 2006-05 |
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M. Martínez, S. Bracho
"Design of a Microelectronic Circuits Course Using Interactive Methods"
IEEE International Conference on Microelectronic System Education. Anaheim (CA-USA). 2005-06 |
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M. Martínez, S. Bracho
"Métodos interactivos de aprendizaje a distancia aplicados a los Sistemas Electrónicos."
6º Simposium Internacional de Informatica Educativa (SIIE04). Caceres (E). 2004-11 |
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M. Allende, R. Mozuelos, M. Martínez, S. Bracho
"Distance access to test equipment in an on-line IC test course"
Microelectronics Education, EWME 2002. Universidad de Vigo (España)
Marcombo Boixareu Editores. 2002-05 |
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|
R. Mozuelos, M. Allende, M. Martínez, S. Bracho
"Laboratorio Remoto de Test: Caracterización de un Convertidor Analógico - Digital"
V Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE 2002). Las Palmas de Gran Canaria. 2002-02 |
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Y. Lechuga, F. Azcondo, M. Martínez, S. Bracho
"Resultados del empleo de Internet en asignaturas de la Ingeniería Industrial"
V Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE 2002). Las Palmas de Gran Canaria. 2002-02 |
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M. Allende, R. Mozuelos, M. Martínez, S. Bracho
"On line IC test course with distance access to test equipment"
2nd IEEE Latin American Test Workshop. Cancún (Mexico). 2001-02 |
|
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|
R. Mozuelos, M. Martínez, S. Bracho
"Test Laboratory"
1st Workshop of Test Network SetNet. Newcastle (UK). 2000-10 |
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|
M. Valderrama, F. Azcondo, F. Díaz
"Entorno de Instrumentación Basado en el Estándar IEEE 488 Aplicado a la Medida del Control de un Motor Trifásico Asíncrono en las Prácticas de Electrónica Industrial"
IV Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE 2000). Barcelona. 2000-09 |
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Y. Lechuga, M. Martínez, S. Bracho
"Una experiencia de empleo de Internet en la enseñanza de la asignatura Sistemas Electrónicos en la Ingeniería Industrial"
IV Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE 2000). 2000-09 |
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M. Martínez, F. Azcondo, S. Bracho
"A web application experience in electronic education in the enginnering syllabus"
3rd European Workshop on Microelectronics Education (EWME´00). Aix-in-Provence (France). 2000-05 |
|
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F. Azcondo, R. Casanueva, M. Martínez, S. Bracho, L. González, G. Ateca
"Tutorial Multimedia para la Enseñanza del Diseño y Test de Circuitos Integrados"
I Certamen Iberoamericano de Tecnologías Aplicadas a la Enseñanza de la Electrónica (CITA98). Madrid. 1998-09 |
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L. González, M. Allende, S. Bracho
"Un Método para la Enseñanza Práctica de los Filtrros SC en las Asignaturas de Laboratorio"
III Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE´98). Madrid. 1998-09 |
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R. Casanueva, F. Azcondo, M. Martínez, S. Bracho
"Multimedia Training on Integrated Circuit Design with Low Cost Hardware"
2nd European Workshop on Microelectronics Education (EWME98). Noordwijkerhout (The Netherlands). 1998-05 |
|
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E. Villar
"Associate Centres: University of Cantabria, Faculty of Industrial and Telecommunication Engineering, Microelectronics Engineering Group"
ECSI Letter, Nº 15, pág. 3. 1998-04 |
|
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|
A. Modino, R. Casanueva, F. Azcondo, M. Martínez, S. Bracho
"Enseñanza Multimedia del Diseño Microelectrónico con Celdas Estándares"
Información Tecnológica, Vol. 9, Nº. 1, págs. 131-136. 1998-01 |
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R. Casanueva, F. Azcondo, M. Martínez, S. Bracho
"Multimedia Training on Integrated Circuits Design with Low Cost Hardware"
Microelectronics Education. Ed. Kluwer Academic Publishers. 1998-01 |
|
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|
A. Modino, R. Casanueva, F. Azcondo, M. Martínez, S. Bracho
"Introducción de Tecnologías Multimedia en la Enseñanza de la Microelectrónica"
II Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE96). Sevilla. 1996-09 |
|
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|
S. Bracho, M. Martínez, F. Azcondo
"Experiencias sobre formación en el diseño VLSI de la Universidad de Cantabria"
1er Workshop de IBERCHIP. Cartagena de Indias (Colombia). 1995-02 |
|
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|
P. Sánchez, E. Villar
"Docencia del VHDL: Experiencia en la E.T.S.I. Industriales y de Telecomunicación de la Universidad de Cantabria"
Jornadas de Tecnología Electrónica JTEC95. Las Palmas. 1995-02 |
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| Diseño de sistemas embebidos HW/SW |
|
J. Pérez, Angels Salvador, Josep Vidal, Unai Sanchez, Nuria Pastor, Ruthy Acosta, Silvia Narejos, Danielle Morrison, Francesc Lopez
"Telemedicine in the face of the COVID-19 pandemic"
Atención Primaria. 2020-04 |
|
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|
F. Herrera, E. Villar
"CONTREP: A single-source framework for UML-based
Modelling and Design of Mixed-Criticality Systems"
University Booth in DATE 2016. 2016-03 |
|
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|
F. Herrera
"UML/MARTE modelling for mixed-criticality systems"
Tutorial "CONTREX: Virtual Integration Testing for Mixed-Criticality Systems under Consideration of Power and Temperature Constraints" in HIPEAC 2016. 2016-01 |
|
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|
F. Herrera, P. Peñil, E. Villar
"Enhancing Analyzability and Time Predictability in UML/MARTE Component-based Application Models"
Forum on specification & Design Languages (FDL 2015). 2015-09 |
|
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|
F. Herrera, Ingo Sander, Kathrin Rosvall, Edoardo Paone, Gianluca Palermo
"An Efficient Joint Analytical and Simulation-based Design Space
Exploration Flow for Predictable Multi-Core Systems"
7th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools. RAPIDO´15. 2015-01 |
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Á. Díaz, J. González, P. Sánchez, P. González
"Virtual platform for power and security analysis of wireless sensor network"
SPIE 2013. 2013-04 |
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Á. Díaz, P. Sánchez, J. Sancho, J. Rico
"Simulation of attacks in Wireless Sensor Network"
DCIS 2012. 2012-11 |
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F. Herrera, H. Posadas, E. Villar, D. Calvo
"Enhanced IP-XACT Platform Descriptions for Automatic Generation from UML/MARTE of Fast Performance Models for DSE"
15th Euromicro Conference on Digital System Design, DSD'2012. 2012-09 |
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K. Gruttner, P.A. Hartmann, K. Hylla, S. Rosinger, W. Nebel, F. Herrera, E. Villar, C. Brandolese, W. Fornaciari, G. Palermo, C. Ykman-Couvreur, D. Quaglia, F. Ferrero, R. Valencia
"COMPLEX - COdesign and power Management in PLatform-based design space EXploration
"
15th Euromicro Conference on Digital System Design, DSD'2012. 2012-09 |
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F. Herrera, P. Peñil, E. Villar, F. Ferrero (GMV), R. Valencia (GMV)
"An Embedded System Modelling Methodology for Design Space Exploration
"
III Jornadas de Computación Empotrada, Sarteco 2012. 2012-09 |
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F. Herrera, P. Peñil, H. Posadas, E. Villar
"A Model-Driven Methodology for the Development of SystemC Executable Environments
"
Proceedings of the 2012 Forum on Specification and Design Languages, FDL'2012, IEEE. 2012-09 |
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Á. Díaz, R. Diego, P. Sánchez
"Virtual Platform for Wireless Sensor Network"
DSD Euromicro 2012. 2012-09 |
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C. Silvano, W. Fornaciari, G. Palermo, V. Zaccaria, F. Castro, M. Martínez, S. Bocchio, R. Zafalon, P. Avasare, G. Vanmeerbeeck, C. Ykman-Couvreur, M. Wouters, C. Kavka, L. Onesti, A. Turco, U. Bondi, G. Mariani, H. Posadas, E. Villar, C. Wu, F. Dongrui, Z. Hao
"The MULTICUBE Design Flow"
C. Silvano, W. Fornaciari & E. Villar (Eds.): "Multi-objective Design Space Exploration of Multiprocessor SoC Architectures: the MULTICUBE Approach", Springer, New York, USA. 2011-10 |
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F. Herrera, E. Villar, Philipp Harmann
"SystemC Refinement of Abstract Adaptive Processes for Implementation into Dynamically Reconfigurable Hardware
"
Proceedings of the Forum of Design and Specification Languages 2011 (FDL'2011). 2011-09 |
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F. Herrera, P. Peñil, E. Villar, F. Ferrero (GMV), R. Valencia (GMV), L. Lavagno (PoliTo), D. Quaglia (EdaLab)
"SystemC Generation Tools from MARTE and Stateflow"
Deliverable D2.1.2 of the COMPLEX project. 2011-06 |
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Emmanuel Vaumorin (Magillem), Bart Vanthournout (Synopsys), Sara Bocchio (ST-I), Davide Quaglia (EdaLab), F. Herrera, P. Peñil, E. Villar, Kai Hylla (OFFIS), Tiemo Fandrey (OFFIS)
"Preliminary report on virtual system generation"
Deliverable D2.5.1 of the COMPLEX project. 2011-06 |
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Carlo Brandolese (PoliMi), Gianluca Palermo (PoliMi), William Fornaciari (PoliMi), F. Herrera, H. Posadas, E. Villar, Massimo Poncino (PoliTo), Chantal Ykman-Couvreur (IMEC)
"Preliminary report on design space exploration"
Deliverable 3.4.1 of COMPLEX project. 2011-06 |
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Carlo Brandolese (PoliMi), Gianluca Palermo (PoliMi), William Fornaciari (PoliMi), F. Herrera, E. Villar, Francisco Ferrero (GMV), Raúl Valencia (GMV), Bart Vanthournout (Synopsys)
"Preliminary report on Embedded Software Estimation and Model Generation
"
Deliverable D2.2.1 of the COMPLEX project. 2010-12 |
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Kai Hylla (OFFIS), Saif A. Butt (CV), F. Herrera, S. Real, P. González, P. Sánchez
"Preliminary report on Custom Hardware Estimation and Model Generation
"
Deliverable D2.4.1 of the COMPLEX project. 2010-12 |
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L. Diaz, H. Posadas, E. Villar
"Obtaining Memory Address Traces from Native Co-Simulation for Data Cache Modeling in SystemC"
XXV Conference on Design of Circuits and Integrated Systems, DCIS'10. 2010-11 |
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D. Calvo, E. Villar, A. Aquaviva, E. Macii
"An Approach For High-Level Thermal Modeling using Native Simulation"
EUROMICRO Conference on Digital Systems Design. 2010-09 |
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E. Villar
"SW simulation and Performance Analysis in Multi-Processing Embedded Systems"
ARTEMIS Technology Conference, Budapest, Hungary. 2010-06 |
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H. Posadas, S. Real, E. Villar
"Refined Performance and Power Estimation Prototype Tool"
Deliverable D2.1.2 of the FP7 216693 MULTICUBE Project. 2010-02 |
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H. Posadas, G. de Miguel, E. Villar
"Initial Performance and Power Estimation Prototype Tool"
Deliverable D2.1.1 of the FP7 216693 MULTICUBE Project. 2009-02 |
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| Especificación de sistemas embebidos |
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F. Mallet, E. Villar, F. Herrera
"MARTE for CPS and CPSoS"
in S. Nakajima, J.P. Talpin, M. Toyoshima and H. Yu (Eds.): "Cyber-Physical System Design from an Architecture Analysis Viewpoint: Communications of NII Shonan Meetings", Springer, pp.81-108, doi="10.1007/978-981-10-4436-6. 2017-05 |
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F. Herrera, P. Peñil, E. Villar
"UML/MARTE Modelling for Design Space
Exploration of Mixed-Criticality Systems on top
of Time-Predictable HW/SW Platforms"
Jornadas de Computación Empotrada (JCE15). 2015-09 |
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F. Herrera, H. Posadas, E. Villar, D. Calvo
"Enhanced IP-XACT Platform Descriptions for Automatic Generation from UML/MARTE of Fast Performance Models for DSE"
15th Euromicro Conference on Digital System Design, DSD'2012. 2012-09 |
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K. Gruttner, P.A. Hartmann, K. Hylla, S. Rosinger, W. Nebel, F. Herrera, E. Villar, C. Brandolese, W. Fornaciari, G. Palermo, C. Ykman-Couvreur, D. Quaglia, F. Ferrero, R. Valencia
"COMPLEX - COdesign and power Management in PLatform-based design space EXploration
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15th Euromicro Conference on Digital System Design, DSD'2012. 2012-09 |
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F. Herrera, I. Ugarte
"Concurrent Specification of Embedded Systems: An Insight into the Flexibility vs Correctness trade-off
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Kiyofumi Tanaka: "Embedded Systems - Theory and Design Methodology", InTech, Croatia. 2012-02 |
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F. Herrera, P. Peñil
"An Eclipse-based Framework for Modelling and Design Space
Exploration of Embedded Systems: The COMPLEX approach
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2nd Spanish Eclipse Embedded's Day. 2011-10 |
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F. Herrera, P. Peñil, E. Villar, F. Ferrero (GMV), R. Valencia (GMV), L. Lavagno (PoliTo), D. Quaglia (EdaLab)
"SystemC Generation Tools from MARTE and Stateflow"
Deliverable D2.1.2 of the COMPLEX project. 2011-06 |
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Emmanuel Vaumorin (Magillem), Bart Vanthournout (Synopsys), Sara Bocchio (ST-I), Davide Quaglia (EdaLab), F. Herrera, P. Peñil, E. Villar, Kai Hylla (OFFIS), Tiemo Fandrey (OFFIS)
"Preliminary report on virtual system generation"
Deliverable D2.5.1 of the COMPLEX project. 2011-06 |
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Carlo Brandolese (PoliMi), Gianluca Palermo (PoliMi), William Fornaciari (PoliMi), F. Herrera, H. Posadas, E. Villar, Massimo Poncino (PoliTo), Chantal Ykman-Couvreur (IMEC)
"Preliminary report on design space exploration"
Deliverable 3.4.1 of COMPLEX project. 2011-06 |
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Francisco Ferrero (GMV), R. Valencia (GMV), F. Herrera, E. Villar, L. Lavagno, D. Quaglia
"System specification methodology using MARTE and Stateflow
"
Deliverable D2.1.1 of the COMPLEX project.. 2010-12 |
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| Verificación de sistemas embebidos |
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P. González, P. Sánchez
"Towards a Verification Flow Across Abstraction Levels: Verifying Implementations Against Their Formal Specification"
TCAD. 2017-03 |
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Carlo Brandolese (PoliMi), Gianluca Palermo (PoliMi), William Fornaciari (PoliMi), F. Herrera, E. Villar, Francisco Ferrero (GMV), Raúl Valencia (GMV), Bart Vanthournout (Synopsys)
"Preliminary report on Embedded Software Estimation and Model Generation
"
Deliverable D2.2.1 of the COMPLEX project. 2010-12 |
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Kai Hylla (OFFIS), Saif A. Butt (CV), F. Herrera, S. Real, P. González, P. Sánchez
"Preliminary report on Custom Hardware Estimation and Model Generation
"
Deliverable D2.4.1 of the COMPLEX project. 2010-12 |
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